Multiple instantiation system

Details Multiple instantiation system Multiple instantiation system

1998-10-20

2004-04-27

Broda, Samuel (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C714S741000, C714S039000

Reexamination Certificate

active

06728667

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a method of simultaneously conducting simulation testing of a number of simulated electronic device designs each having essentially identical sequences of instructions.
BACKGROUND OF THE INVENTION
Cycle-based simulation software is used to simulate electronic devices to decrease the cost and complexity of building large electronic systems, microprocessors, and ASICs. Such simulation software is typically much faster than event-driven simulators, and has performance levels that approach those of more expensive hardware accelerators.
One cycle-based simulation software product, SpeedSim/3 available from Quickturn Design Systems -Advanced Simulation Division of Chelmsford, Mass., is able to perform up to 32 tests simultaneously on one image of the design model on a single workstation. This technique of simultaneously running multiple diagnostics or application program streams has a theoretical improvement of 32 times performance, and a typical actual 5 to 10 times performance gain in total throughput.
In multi processor based designs, a number of identical processors communicate with a common memory. The boolean logic streams used to simulate such processors is virtually identical, while still allowing for differences, due in part to the personality pins of the processors.
With prior art cycle-based simulation software, one word of the memory device used in the simulation testing is used to store the results of a single simulation test. Thus, a four word memory device would allow up to four simultaneous tests to be run. The number of simultaneous tests, and thus by definition the speed with which testing occurs, is thus constrained by the particular memory device used.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a simulation testing method which reduces the effective network size, thus increasing capacity and performance.
It is a further object of this invention to provide a simulation testing method in which a number of simultaneous tests can be run, the number of such simultaneous tests equal to the total number of bits in a row of the memory device used to store test results, regardless of the number of words in the row.
This invention features methods of simultaneously conducting simulation testing of a plurality of simulated electronic device designs using cycle-based software which is capable of simultaneously executing a plurality of simulation tests along separate test pathways for each simulated device, in which the simulated device designs each comprise essentially identical sequences of instructions. The basic method includes the steps of providing a memory device which holds a matrix of memory bits, in which each row of the matrix holds a plurality of data words each made up of a plurality of bits.
A single bit location of the data words of the memory device is then designated for each test of each simulated device. The designated bit locations may be grouped into a number of groups equal to the number of simulated electronic device designs being tested. The simulation test on each simulated device design is then conducted.
During the conduct of the simulation tests, the test results for each test are stored in the designated bit location for the test, to allow testing to simultaneously occur along one or more test pathways for each simulated electronic device design, with the quantity of such simultaneous tests equal to no more than the number of bits in a row of the matrix of memory bits of the memory device.
In the preferred embodiment, the same number of simultaneous tests are conducted on each simulated device. Preferably, a number of simultaneous tests are conducted on each simulated device. That number may equal the number of bits in a data word of the memory device, in which case a single data word is used to store test results for each simulated device.
DESCRIPTION OF THE PREFERRED EMBODIMENT
This invention may be accomplished in methods of simultaneously conducting simulation testing of a plurality of simulated electronic device designs, in which the simulated device designs each comprise essentially identical sequences of boolean instructions. Cycle-based simulation software, which is capable of simultaneously executing a plurality of simulation tests along separate test pathways for each simulated device, is used in the invention. The invention also uses a memory device which holds a matrix of memory bits, in which each row of the matrix holds a plurality of data words each made up of a plurality of bits. Typically, the memory (32 or 64 bit) holds a matrix of either 4 or 8, 8 bit words.
A single bit location of those data words of the memory device is designated for each test of each simulated device. These designated bit locations may be grouped into a number of groups equal to the number of simulated electronic device designs being tested. During the conduct of the simultaneous simulation tests, the test results for each test are stored in the designated bit location for that particular test. This allows testing to simultaneously occur along one or more test pathways for each simulated electronic device design, with the quantity of such simultaneous tests equal to no more than the number of bits (typically 32 or 64) in a row of the matrix of memory bits of the memory device.
There are times in which it is desirable to perform simultaneous simulation tests of multiple instantiations of simulated device designs. An example would be in multi processor based designs, in which multiple identical processors communicate with a common memory. The boolean logic representing these processors is identical, or at least virtually identical; there may be slight differences in the logic depending on differences in the personality pins of the processors being simulated, which do not affect this invention. This invention results in faster simulation testing of such multiple processor based designs. Network switches also have a high degree of identical logic, making them good candidates for this invention as well.
The preferred method of this invention contemplates the use of a memory device which holds a matrix of memory bits. In the preferred embodiment, the invention employs a 32 bit memory array that holds four, 8 bit words per row. Obviously, other memory devices can be used. In the method of this invention, a single bit of the 32 bits available in the memory is designated for each test of each simulated device. Since the logic is boolean, a single bit is sufficient for each test; there is no interaction between the tests. This same bit in each row of the memory device is used exclusively and only for that particular test. This allows a number of simultaneous tests to be run which is equal to the number of bits available in a row of the memory device. In the preferred embodiment, then, up to 32 simultaneous tests can be run.
In one non-limiting example of the application of the method of this invention, it is desired to simulate four instances, which may be simulations of four virtually identical processors. With a 32 bit memory device, up to 32 simultaneous tests can be run. Thus, it is possible to run eight simultaneous tests on each of the four instances. It is not a limitation of this invention that the same number of simultaneous tests are accomplished on each instance. Rather, this invention allows simultaneous testing of multiple instantiations, whether there is one, or more than one, simulation test being simultaneously accomplished on each instance.


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