Multiple-input, single-exit delay line architecture

Details Multiple-input, single-exit delay line architecture Multiple-input, single-exit delay line architecture

2007-02-06

2007-02-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S277000

Reexamination Certificate

active

10950608

ABSTRACT:
A delay line includes a delay chain consisting of series-connected NAND gate delay stages with a delayed output signal extracted from the final delay stage. Tap decode gates are preferably used to “inject” the input signal to be delayed into the delay chain using one input of the NAND gate delay stage, referred to as an “injection point.” The desired delay is achieved by selecting an injection point relative to the final delay stage, or exit point, of the delay chain. Selection of an injection point is provided by the binary decode of a tap address that activates the injection NAND gate delay stage, allowing the injected signal to propagate from the activated injection point to the exit point of the delay chain.

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