Multiple-input multiple-output decoding circuit

Details Multiple-input multiple-output decoding circuit Multiple-input multiple-output decoding circuit

1987-11-17

1989-09-12

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307585, 341 50, H03K 19177

Patent

active

048663050

ABSTRACT:
A decoding circuit comprises an m row by n column matrix arrangement of transmission gates, wherein an output terminal of one of two mutually adjacent transmission gates in each column of the matrix arrangement is connected to an input terminal of the other of the two mutually adjacent transmission gates, input terminals of the n transmission gates in a last row are connected to a high voltage source, output terminals of the n transmission gates in a first row are connected to a low voltage source, and gates of the transmission gates are connected so that all of the n transmission gates in a predetermined row are simultaneously turned OFF responsive to an n-bit input code having a predetermined value.

REFERENCES:
patent: 4350905 (1982-09-01), Sato
patent: 4453096 (1984-06-01), Le Can et al.
patent: 4607176 (1986-08-01), Burrows et al.
patent: 4617477 (1986-10-01), DePaolis, Jr.
patent: 4684829 (1987-08-01), Uratani
patent: 4710649 (1987-12-01), Lewis
patent: 4739195 (1988-04-01), Masaki

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