Multiple input frequency memory controller

Details Multiple input frequency memory controller Multiple input frequency memory controller

1991-09-11

1994-07-26

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642618, 3642702, G06F 9305

Patent

active

053332938

ABSTRACT:
A synchronous memory controller capable of operating with three different frequency microprocessors and yet providing similar DRAM timings. Input frequencies of 32, 25 and 33 MHz correspond to 16, 25 and 33 MHz microprocessors. Various states are bypassed at certain frequencies to allow the various memory, latch and buffer control signals to be produced uniformly. The memory controller also handles operations from external buses, such as the EISA and ISA buses at the various input frequencies. These external bus cycles are controlled by separate state machines, which also have states bypassed for certain input frequencies.

REFERENCES:
patent: 4014006 (1977-03-01), Sorensen et al.
patent: 4095267 (1978-06-01), Morimoto
patent: 4821229 (1989-04-01), Jauregui
patent: 5086387 (1992-02-01), Arroyo et al.
patent: 5097437 (1992-03-01), Larson
patent: 5179667 (1993-01-01), Iyer

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