Multiple input dissymmetric latch

Details Multiple input dissymmetric latch Multiple input dissymmetric latch

1985-10-23

1987-09-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307279, 307291, H03K 3284, H03K, H03K 1902, H03K 326, H03K 329

Patent

active

046957430

ABSTRACT:
An integrated circuit latch is provided for providing first and second output signals, each first output signal being a logical complement of a corresponding second output signal; the latch includes means for receiving a first clock signal; means for receiving a corresponding second clock signal, the second clock signal being a logical complement of the first clock signal; means for receiving N first data signals, where N is an integer and N<1; means for receiving N second data signals, where each second data signal corresponds to a first data signal and is the logical complement of a corresponding first data signal; NOR-OR logic function means for providing the first output signal characterized by the OR function of first and second logic inputs, the first logic input characterized by the NOR function of the second output and the second clock signal, the second logic input characterized by the NOR function of the first data signals and the first clock signal; and NAND-AND logic function means for providing the second output signal characterized by the AND function of third and fourth logic inputs, the third logic input characterized by the NAND function of the first output signal and the first clock signal, said fourth logic input characterized by the NAND function of the second data signals and the second clock signal.

REFERENCES:
patent: 3845330 (1974-10-01), Colonel
patent: 4514649 (1985-04-01), Nuzillat et al.
patent: 4518871 (1985-05-01), Toyoda et al.
Tech. Notes, RCA, "TTL to CMOS Buffer Circuit", Dingwall, TN No. 1114, Jun. 11, 1975.

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