Multiple input CMOS logic circuits

Details Multiple input CMOS logic circuits Multiple input CMOS logic circuits

1990-07-31

1991-09-03

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307449, 307279, H03K 19094

Patent

active

050457233

ABSTRACT:
A multiple input CMOS logic circuit includes a bistable input section with two nodes. In an inactive state, the input section maintains the nodes at opposite CMOS logic levels. In an active state, the nodes are maintained at substantially equal levels positioned between the two CMOS logic levels. The input circuit includes a set of parallel CMOS transistor pairs, cross connected at the nodes. The CMOS pairs are unbalanced by inequality of transistor gate widths. The imbalance causes the input circuit to assume the inactive state. A plurality of input CMOS transistors are connected in parallel between the nodes and receive input signals at their gates. When any of the input transistors is turned on by a change of input signal state, it conducts between the nodes, causing the input circuit to transition to the active state. An output buffer connected to the nodes translates the node levels to CMOS signal levels.

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Abstract for 1050099, Soviet Union, English Translation.
Abstract for 1064445, Soviet Union, English Translation.

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