Multiple input buffers for address bits

Details Multiple input buffers for address bits Multiple input buffers for address bits

1995-01-10

2000-05-30

Lane, Jack A.

Static information storage and retrieval

Interconnection arrangements

365 51, 36523003, 36523008, G11C 502, G11C 506

Patent

active

060698144

ABSTRACT:
An input architecture for supply a plurality of signals to a plurality of circuit blocks located in an interior of an integrated circuit device. A plurality of unbuffered signal lines are each connected between a bondpad area and all of a plurality of input buffers. The input buffers are located adjacent to and connected to the plurality of circuit blocks instead of being located at the periphey of the integrated circuit adjacent the bondpad area.

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