Multiple generating register

Details Multiple generating register Multiple generating register

1975-12-22

1977-07-05

Malzahn, David H.

Registers

Transfer mechanism

Traveling pawl

G06F 752

Patent

active

040341984

ABSTRACT:
A multiple-generating register generates one of several possible multiples of a binary member which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circuit for generating the multiple-generating commands in response to a three-bit control signal and comprises further a plurality of selector latch logic circuits. Each selector latch logic circuit receives as a first input a respective bit of the input binary number and receives as a second input the next lowest order bit of the input binary number, except that the selector latch logic circuit which receives as a first input the lowest order bit of the input binary number receives as a second input a zero-valued binary bit. The plurality of selector latch logic circuits generate a binary number that is a multiple of the input binary number, which multiple is equal to the input binary number times .+-.1, .+-.2, or 0, depending upon the informational content of the three-bit control signal.

REFERENCES:
patent: 3372269 (1968-03-01), MacSorley et al.
patent: 3691359 (1972-09-01), Dell et al.
patent: 3949209 (1976-04-01), Fett
C. Ghest, "Multiplying Made Easy for Digital Assemblers", Electronis, pp. 56-61, Nov. 22, 1971.

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