Multiple-gate transistors with improved gate control

Details Multiple-gate transistors with improved gate control Multiple-gate transistors with improved gate control

2005-01-18

2005-01-18

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S216000, C438S421000

Reexamination Certificate

active

06844238

ABSTRACT:
A method for fabricating a multiple-gate device including the steps of providing a substrate of a semi-conducting layer on an insulator stack which includes an insulator layer overlying an etch-stop layer; patterning a semi-conducting layer forming a semiconductor fin; etching the insulator layer at the base of the fin forming an undercut; depositing a gate dielectric layer overlying the fin; depositing an electrically conductive layer over the gate dielectric layer; etching the electrically conductive layer forming a gate straddling across the two sidewall surfaces and the top surface of the fin; and forming a source region and a drain region in the fin.

REFERENCES:
patent: 6514808 (2003-02-01), Samavedam et al.
patent: 6521949 (2003-02-01), Assaderaghi et al.
patent: 6596599 (2003-07-01), Guo
patent: 20030011080 (2003-01-01), Deshpande et al.
patent: 20030111678 (2003-06-01), Colobuo et al.

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