Multiple gate transistor architecture providing an...

Details Multiple gate transistor architecture providing an... Multiple gate transistor architecture providing an...

2011-07-19

2011-07-19

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S401000

Reexamination Certificate

active

07982243

ABSTRACT:
The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

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Notice of Allowance for U.S. Appl. No. 11/532,725 mailed Jul. 29, 2008.

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