Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2003-02-28
2004-11-09
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S066000, C257S213000, C257S262000, C257S347000, C257S350000
Reexamination Certificate
active
06815738
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a strained silicon strip on a supporting platform. In particular the invention relates to a method for producing a multifaceted gate MOSFET transistor using a tensilely strained Si strip on an insulator. The invention also teaches a method for fabricating processors which comprise the disclosed method for producing the strained silicon layer multifaceted gate MOSFETs.
BACKGROUND OF THE INVENTION
Today's integrated circuits include a vast number of devices. Smaller devices are key to enhance performance and to improve reliability. As MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor, a name with historic connotations meaning in general an insulated gate Field-Effect-Transistor) devices are being scaled down, however, the technology becomes more complex and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. In this regard the semiconductor that has progressed the farthest is the primary semiconducting material of microelectronics: silicon (Si).
There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Several avenues are being explored for keeping device performance improvements on track. Among these is the use of tensilely strained Si as the basic semiconducting device material. The strained Si layer is typically formed by growing Si epitaxially over a relaxed graded SiGe (Ge stands for germanium) based layer as discussed, for instance, in Materials Science and Engineering Reports R17, 105 (1996), by P. M. Mooney, and in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: “Low Defect Density/arbitrary Lattice Constant Heteroepitaxial Layers” incorporated herein by reference. Tensile strain in the Si has significant advantages. For instance, a heterostructure consisting of relaxed Si
0.7
Ge
0.3
capped with a thin (20 nm) strained Si layer has electron and hole mobilities over 80% higher than bulk Si. The higher mobility leads to faster switching speed, higher “on” current, and lower power dissipation. MOSFETs fabricated in tensile strained Si exhibits higher carrier mobilities than conventional MOSFET as it was shown, for instance, in “NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures”, by Welser, J. et al., 1992 IEDM Tech Dig., pp. 1000-1002. Fabrication of a tensilely strained Si layer is also taught in US patent application titled: “Strained Si based layer made by UHV-CVD, and Devices Therein”, by J. Chu et al, filed Feb. 11, 2002, Ser. No. 10/073,562, incorporated herein by reference.
Strained-Si layers are the result of biaxial tensile stress induced in silicon grown on a substrate formed of a material whose lattice constant is greater than that of silicon. The lattice constant of germanium is about 4.2% greater than that of silicon, and the lattice constant of a silicon-germanium alloy is linear with respect to its germanium concentration. As a result, the lattice constant of a SiGe alloy containing fifty atomic percent germanium is about 2% greater than the lattice constant of silicon. Epitaxial growth of silicon on such a SiGe substrate will yield a silicon layer under tensile strain, with the underlying SiGe substrate being essentially unstrained, or “relaxed.”
A structure and process that realizes the advantages of a strained-Si channel structure for MOSFET application is taught in the commonly-assigned U.S. Pat. No. 6,059,895 to Chu et al., incorporated herein by reference, which discloses a technique for forming a CMOS device having a strained-Si channel on a SiGe layer, all on an insulating substrate. Since most commonly the semiconducting layer in which devices are fabricated is Si, the technology carries the terminology of SOI (Si on insulator), and the buried insulator is SiO
2
, to yield the name of BOX (buried oxide).
However, there are still many outstanding issues in achieving the highest possible performance in deeply submicron MOSFET devices. With shortening gate lengths, the so called short channel effects, most notably the “drain induced barrier lowering” (DIBL) pose severe roadblocks to miniaturization. These effects can be mitigated by introducing basic structural changes in the devices, leading to the use of multiple gates. However, this approach can only yield the desired performance improvements if it is appropriately coupled with other high performance techniques, such as with strained Si and with SOI, a problem that is still looking for solutions.
SUMMARY OF THE INVENTION
In view of the problems discussed above this invention discloses a method for fabricating multifaceted, or multiple gated MOSFET devices, (commonly known as FinFET devices) in a tensilely strained Si on an insulator. Such a device is not simply a planar structure conducting on one surface, but conducting on more than one side, or facet on the surface of a device body. The reasons that a multifaceted gate device can be downscaled further than a regular planar device are relatively complex, but they have been already given in the technical literature, for instance in: “Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFET's at the 25 nm Channel Length Generation,” by H.-S. P. Wong, et al, 1998 IEDM Tech Dig., pp. 407-10.
The distinct advantages of a strained Si FinFET could be best realized with a strained-Si structure that does not include the strain-inducing layer, but instead has a strained-Si layer that is directly on another layer, such as an insulator layer to yield a strained SOI structure. Conventional wisdom has been that the SiGe layer must be present at all times to maintain the strain in the silicon layer. However, such is not the case, as was disclosed in the US patent application “Method of Forming Strained Silicon on Insulator and Structures Formed Thereby” by K. Rim, filed on Mar. 31, 2001, Ser. No. 09/823,855, incorporated herein by reference.
Accordingly, it is the object of the present invention to teach a method by which a strained material strip on a support platform can be fabricated.
It is also an object of the present invention to teach a method to have such a strip of Si made suitable for FinFET fabrication.
It is a further object of the present invention to teach a method for FinFET fabrication with strained Si.
And furthermore, the present invention teaches a method for fabricating a processor which comprises the strained Si FinFET devices produced by the disclosed method.
REFERENCES:
patent: 6059895 (2000-05-01), Chu
patent: 6458662 (2002-10-01), Yu
patent: 6475869 (2002-11-01), Yu
patent: 6602613 (2003-08-01), Fitzgerald
Louie Wai-Sing
Sai-Halasz George
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