Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-09-04
2007-09-04
Fourson, George R. (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S164000, C438S197000, C257SE29028, C257SE21236, C257SE21377
Reexamination Certificate
active
11240243
ABSTRACT:
A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.
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Mathew Leo
Rao Rajesh A.
Clingan, Jr. James L.
Dolezal David G.
Fourson George R.
Freescale Semiconductor Inc.
Maldonado Julio J.
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