Multiple event hardened core memory

Details Multiple event hardened core memory Multiple event hardened core memory

1981-11-06

1984-08-07

Smith, Jerry

Excavating

371 51, G06F 1100

Patent

active

044647522

ABSTRACT:
A computer system is provided for reconstructing a word, which is altered during cycling of the computer memory when a nuclear event occurs. The computer system includes a nuclear event detector, a circuit for setting flags in response to the detection of an event, a generating circuit for generating a random variable time interval in response to the flags, a circuit for performing block parity on the data in the memory in response to the flags, and correcting circuit for correcting the altered word in the memory in response to the block parity circuit. The computer system further includes a circuit for correcting multiple memory word upsets in response to the block parity circuit and an updating circuit for performing block parity during sequential storage or random storage of the data words before or after an event.

REFERENCES:
patent: 4031374 (1977-06-01), Groudan et al.
patent: 4037091 (1977-07-01), Beuscher
patent: 4335458 (1982-06-01), Krol
patent: 4358848 (1982-11-01), Patel
patent: 4371963 (1983-02-01), Edwards et al.
patent: 4413327 (1983-11-01), Sabo et al.

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