Multiple digital clock edge generator circuit and method

Details Multiple digital clock edge generator circuit and method Multiple digital clock edge generator circuit and method

1992-09-01

1994-11-22

Wolfe, Willis R.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327259, 327295, 327141, H03K 5153, H03K 504

Patent

active

053672046

ABSTRACT:
A circuit for generating multiple clock edges from a single input clock is disclosed. This circuit has a digital clock input which causes a capacitor to charge and discharge with constant current sources, providing a linear voltage ramp. This linear voltage ramp is monitored by several comparators, each of which have a different reference voltage level, the outputs of which provide the multiple clock edges needed. In this manner, several outputs are generated, each of which has the same fundamental frequency as the input clock signal, but with varying duty cycles and delays from the clock edges of the input clock. In this manner, several clock edges are available for use in synchronous digital systems such as state machines that require precise timing relationships between inputs and clock signals.

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