Multiple differential pair transistor architecture having...

Details Multiple differential pair transistor architecture having... Multiple differential pair transistor architecture having...

1999-05-28

2001-04-03

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Logarithmic

C327S359000, C327S361000

Reexamination Certificate

active

06211717

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to multiple differential transistor pair circuits, and more particularly, to linear multiple differential transistor pair circuits.
BACKGROUND OF THE INVENTION
Multiple differential pair circuits consist of N differential pairs of transistors operating in parallel, each having an appropriate input offset voltage. Multiple differential pair circuits are well-known and have many applications, including amplifiers, mixers, filters and other active elements. For a detailed discussion of conventional multiple differential pair circuits implemented in bipolar technology and their applications, see, for example, B. Gilbert, “The Multi-Tanh Principle: A Tutorial Overview,” IEEE J. of Solid-State Circuits, Vol. 33, 2-17 (January 1998), incorporated by reference herein.
FIG. 1
illustrates a conventional multiple differential pair circuit
100
. The illustrative multiple differential pair circuit
100
consists of five (5) differential pairs of transistors
200
-
1
through
200
-
5
coupled in parallel. A representative differential transistor pair circuit
200
is discussed below in conjunction with FIG.
2
. Four (4) of the five (5) differential transistor pair circuits
200
-
1
,
200
-
2
,
200
-
4
,
200
-
5
, each have a corresponding well-defined offset voltage &Dgr;-
1
, &Dgr;-
2
, &Dgr;-
3
, &Dgr;-
4
, shown in FIG.
1
. Thus, the differential transistor pair circuit
200
-
3
in the middle of the multiple differential pair circuit
100
does not have an offset voltage, while the other differential transistor pair circuits
200
-
1
,
200
-
2
,
200
-
4
,
200
-
5
have a corresponding offset, &Dgr;. As the differential transistor pair circuits
200
-N progress away from the center differential transistor pair circuit
200
-
3
, the offset voltage, &Dgr;, increases progressively, taking values of ±&Dgr;, ±2&Dgr; and so on, in a known manner. When configured in this manner, such circuits are referred to as equidistant-offset multiple differential pair circuits.
FIG. 2
is a schematic block diagram of a representative differential transistor pair circuit
200
. The two transistor devices
210
-
1
and
210
-
2
that comprise the differential transistor pair circuit
200
are identical (i.e., perfectly matched), in a known manner. For a given applied voltage, V
IN
, a desired output current, I
1
, I
2
, can be obtained from the differential transistor pair circuit
200
by varying the bias current, I
O
.
Bipolar transistors, and thus, bipolar differential transistor pair circuits
200
, have well-defined voltage-current (V-I) characteristics. Differential transistor pair circuits
200
have been implemented using bipolar transistors (or CMOS transistors operating in sub-threshold ranges where they behave like bipolar transistors), where the voltage-current (V-I) characteristic is exponential.
FIG. 3
illustrates the voltage-current (V-I) characteristic
300
of the differential transistor pair circuit
200
, shown in FIG.
2
. Transistors having exponential voltage-current (V-I) characteristics were thought to be required in order to obtain multiple differential pair circuits
100
having a transconductance, g
m
, that is linearly proportional to the bias current.
As apparent from the above-described deficiencies with conventional multiple differential pair circuits, a need exists for multiple differential pair circuits comprised of pairs of transistors having non-exponential voltage-current (V-I) characteristics. A further need exists for a multiple differential pair circuit that provides both linearity and linear tuning capabilities, independent of the transistor technology.
SUMMARY OF THE INVENTION
Generally, a multiple differential pair circuit is disclosed having a transconductance, g
m
, proportional to the bias current, I
0
, for any transistor technology. According to one aspect of the invention, the transistors utilized to construct each of the differential transistor pairs in a multiple differential pair circuit are permitted to have a non-exponential voltage-current (V-I) characteristic. In one implementation, the transistors are embodied as MOS transistors. The present invention thus allows multiple differential pair circuits with transconductance, g
m
, proportional to bias current to be fabricated in any transistor technology.
As multiple differential pair circuits are linearized, the effective transconductance, g
m
, becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices. Thus, the present invention recognizes that multiple differential pair circuit having a transconductance, g
m
, that is linearly dependent on bias current can be fabricated using any transistor technology. Thus, transistors having an exponential voltage-current (V-I) characteristic are not required. In this manner, the present invention allows multiple differential pair circuits to be migrated from one technology to another without significantly impacting the operation of such multiple differential pair circuits.
Methods and apparatus are disclosed that provide a linear transconductance, g
m
, with respect to the bias current, I
0
, using differential pairs of transistors where each transistor has a non-exponential voltage-current (V-I) characteristic.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.


REFERENCES:
patent: 5319264 (1994-06-01), Kimura
patent: 5602504 (1997-02-01), Liu
B. Gilbert, “The Multi-Tanh Principle: A Tutorial Overview,” IEEE J. of Solid-State Circuits, vol. 33, 2-17 (Jan. 1998).
K. Lasanen et al., “A Structure for Extending the Linear Input Voltage Range of a Differential Input Stage,” Proc. Int'l Conf. of Electronics, Circuits, and Systems, vol. 2, 355-58 (1998).
P. van Lieshout and R. van de Plassche, “A Power-Efficient, Low-Distortion Variable Gain Amplifer Consisting of Coupled Differential Pairs,” IEEE J. of Solid-State Circuits, vol. 32, No. 12, 2105-2110 (1997).

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