Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
1999-02-08
2002-02-26
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S732000, C257S777000
Reexamination Certificate
active
06351028
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the packaging of integrated circuit devices by interposing a plurality of integrated circuit devices within a common package for increased semiconductor device density. More particularly, the present invention relates to multiple integrated circuit devices in a stacked configuration that uses a spacing element allowing increased semiconductor device density and allowing better thermal conductivity for dissipating heat for semiconductor memory devices, semiconductor processor type devices, or any desired type integrated circuit semiconductor device.
2. State of the Art
Integrated circuit semiconductor devices have been known since shortly after the development of the electronic transistor device. The goals in designing and manufacturing semiconductor devices have been to make the devices smaller, more complex, with higher densities, and to include additional features. One method that improves the features and the densities of the semiconductor devices is to shrink the line sizes used in the lithographic process step in fabricating semiconductor devices. For example, each one-half reduction in line width of the circuits of the semiconductor device corresponds to a four-fold increase in chip density for the same size device. Unfortunately, increasing density simply through improved lithographic techniques is limited because of physical limits and the cost factor of scaling down the dimensions of the semiconductor device. Accordingly, alternative solutions to increase semiconductor device density have been pursued. One such alternative has been the stacking of multiple semiconductor devices. However, conventional stacking of semiconductor devices can lead to excessive local heating of the stacked semiconductor devices as well as lead to restraints on how the heat may be removed from the stacked semiconductor devices.
One approach of semiconductor device (die) stacking uses a chip geometry known as cubic chip design and is illustrated in drawing
FIG. 1
(Prior Art). The device
2
includes substrate
4
, upon which a plurality of semiconductor devices
6
is stacked. Each semiconductor device
6
is connected to another semiconductor device and to substrate
4
via bonding elements
8
, which are then encased in a suitable type of resin material
10
forming a package. The semiconductor devices
6
are designed such that an overhanging flange is provided by cutting the edges of a semiconductor device at approximately a 30 to 35-degree angle and inverting the device for the bonding connection. This allows the semiconductor devices
6
to stack one on top of another in a uniform and tight arrangement.
Unfortunately, the cubic design has several disadvantages that make it unsuitable for all types of semiconductor device packaging design. One disadvantage is that the cubic stacking of the semiconductor devices one on top of another causes stack stresses or bending, or both. Additionally, because of stack stressing or bending, there is a limit to the number of semiconductor devices that can be stacked one on top of another. Also, if the adhesive of the stack weakens and comes loose, the semiconductor device will shift, which can result in the breaking of the bonds between the various devices
6
and the substrate
4
. Furthermore, the stacking of the semiconductor devices generates thermal and mechanical problems where the semiconductor devices generate heat that cannot be easily dissipated when they are stacked one upon another.
Additional solutions have been developed in the prior art and are illustrated in U.S. Pat. Nos. 5,585,675 ('675 patent) and 5,434,745 ('745 patent). The '675 patent discloses a packaging assembly for a plurality of semiconductor devices that provides for stacking of the semiconductor devices. The packaging assembly uses angularly offset pad-to-pad via structures that are configured to allow three-dimensional stacking of the semiconductor devices. The electrical connection is provided to a via structure where multiple identical tubes are provided in which a semiconductor device is mounted and then one tube is mounted on top of another tube. The angularly off-set via pads are provided through the stack tube structure for connection. One disadvantage with the angularly offset pad via structure is that the tubes must be precisely manufactured so that the vias are lined up properly. Further, the semiconductor devices must be set within strict tolerances for the tubes to stack one on top of another so the vias can be aligned properly as well.
The '745 patent discloses a stacked semiconductor device carrier assembly and a method for packaging interconnecting semiconductor devices. The carriers are constructed from a metal substrate onto which the semiconductor device attaches. Next, the semiconductor device is wired bonded to the conductor pattern on the substrate and each conductor is routed to the edge of the substrate where it is connected to a half circle of metallized through hole. Again, the '745 patent discloses a tube like design with half circle vias for allowing interconnection to the stack of multiple semiconductor devices.
One disadvantage with the stack type semiconductor device carrier of the '745 patent is that the tubes are connected one with another. Any potential rework operation involving the wire connections is very difficult in that the tube assemblies must be disassembled for such a rework operation.
Accordingly, a multiple stacked arrangement of semiconductor devices and associated methods of stacking that reduce stack stresses or bending of the semiconductor devices, that allow easier reworking of the wiring interconnecting bond pads of the semiconductor devices, that protect the bond pads of each semiconductor device from the other devices, and that effectively remove heat from the semiconductor devices are needed.
SUMMARY OF THE INVENTION
The present invention is directed to the packaging of integrated circuit devices by interposing a plurality of integrated circuit devices within a common package for increased semiconductor device density. The present invention relates to multiple integrated circuit devices in a stacked configuration that uses a spacing element for allowing increased device density and the removal of thermal energy from semiconductor devices and the methods for the stacking thereof.
REFERENCES:
patent: 5434745 (1995-07-01), Shokrgozar et al.
patent: 5515241 (1996-05-01), Werther
patent: 5569956 (1996-10-01), Chillara et al.
patent: 5585675 (1996-12-01), Knopf
patent: 5904497 (1999-05-01), Akram
patent: 6005778 (1999-12-01), Spielberger et al.
patent: 6028365 (2000-02-01), Akram et al.
patent: 63-128736 (1988-06-01), None
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