Multiple die integrated circuit package

Details Multiple die integrated circuit package Multiple die integrated circuit package

2011-05-10

2011-05-10

Chu, Chris (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257SE23039, C257S666000, C257S686000, C438S123000

Reexamination Certificate

active

07939920

ABSTRACT:
A multiple die package and removable storage card is disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator layer. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator layer. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator, at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be electrically coupled via anisotropically conductive areas of the leadframes.

REFERENCES:
patent: 4288841 (1981-09-01), Gogal
patent: 4423468 (1983-12-01), Gatto et al.
patent: 5147815 (1992-09-01), Castro
patent: 5220195 (1993-06-01), McShane et al.
patent: 5239198 (1993-08-01), Lin et al.
patent: 5438224 (1995-08-01), Papageorge et al.
patent: 5715193 (1998-02-01), Norman
patent: 5798564 (1998-08-01), Eng et al.
patent: 5801072 (1998-09-01), Barber
patent: 5861668 (1999-01-01), Cha
patent: RE36077 (1999-02-01), Michii et al.
patent: 5880403 (1999-03-01), Czajkowski et al.
patent: 6051878 (2000-04-01), Akram et al.
patent: 6069025 (2000-05-01), Kim
patent: 6079987 (2000-06-01), Matsunaga et al.
patent: 6080931 (2000-06-01), Park et al.
patent: 6137164 (2000-10-01), Yew et al.
patent: 6153928 (2000-11-01), Cho
patent: 6239496 (2001-05-01), Asada
patent: 6291892 (2001-09-01), Yamaguchi
patent: 6313598 (2001-11-01), Tamba et al.
patent: 6316825 (2001-11-01), Park et al.
patent: 6410355 (2002-06-01), Wallace
patent: 6413798 (2002-07-01), Asada
patent: 6448636 (2002-09-01), Suenaga et al.
patent: 6462421 (2002-10-01), Hsu et al.
patent: 6472732 (2002-10-01), Terui
patent: 6521483 (2003-02-01), Hashimoto
patent: 6603197 (2003-08-01), Yoshida et al.
patent: 6639309 (2003-10-01), Wallace
patent: 6690564 (2004-02-01), Haruta et al.
patent: 6693346 (2004-02-01), Masayuki et al.
patent: 6753207 (2004-06-01), Hur
patent: 6774473 (2004-08-01), Shen
patent: 6815251 (2004-11-01), Akram et al.
patent: 6841876 (2005-01-01), Haruta et al.
patent: 6872903 (2005-03-01), Takenaka et al.
patent: 6951982 (2005-10-01), Chye et al.
patent: 7170158 (2007-01-01), Choi et al.
patent: 2002/0084522 (2002-07-01), Yoshizawa
patent: 2002/0121690 (2002-09-01), Masayuki et al.
patent: 2004/0089717 (2004-05-01), Harari et al.
patent: 2004/0169285 (2004-09-01), Verma et al.
patent: 2006/0102995 (2006-05-01), Tsai et al.
patent: 2007/0096265 (2007-05-01), Wallace
patent: 2007/0096284 (2007-05-01), Wallace
patent: 2008/0050859 (2008-02-01), Wallace
patent: 2009/0239340 (2009-09-01), Wallace
patent: 19522338 (1997-01-01), None
patent: 19648492 (1997-11-01), None
patent: 0798772 (1997-10-01), None
patent: 57063850 (1982-04-01), None
patent: 03030494 (1991-02-01), None
patent: 9326144 (1993-12-01), None
Office Action dated Mar. 9, 2010, Korean Application No. 7013254/2008.
Taiwanese Office Action and Search Report dated Jun. 15, 2009 in Taiwanese Patent Application No. 095140244.
International Search Report dated Jul. 9, 2007 in PCT Application No. PCT/US2006/042450.
“FCBGA (Flip Chip Ball Grid Array)”, 1995 NEC Electronics Corporation, Feb. 6, 2007, http://www.necel.com/pkg/en/pk02—03.html.
Office Action dated Apr. 10, 2007, U.S. Appl. No. 11/264,556, filed Nov. 1, 2005.
Office Action dated Apr. 27, 2007, U.S. Appl. No. 11/264,112, filed Nov. 1, 2005.
Office Action dated Feb. 23, 2007, U.S. Appl. No. 11/264,112, filed Nov. 1, 2005.
Office Action dated Oct. 16, 2007, U.S. Appl. No. 11/264,556, filed Nov. 1, 2005.
Response to Office Action dated Oct. 31, 2007, U.S. Appl. No. 11/264,556, filed Nov. 1, 2005.
Response to Office Action dated Aug. 27, 2007, U.S. Appl. No. 11/264,112, filed Nov. 1, 2005.
Response to Office Action dated Aug. 10, 2007, U.S. Appl. No. 11/264,556, filed Nov. 1, 2005.
Notice of Allowance dated Nov. 9, 2007, U.S. Appl. No. 11/264,556, filed Nov. 1, 2005.
Ex Parte QuayleOffice Action dated Nov. 19, 2007, U.S. Appl. No. 11/264,112, filed Nov. 1, 2005.
Response toEx Parte QuayleOffice Action filed Jan. 22, 2008, U.S. Appl. No. 11/264,112, filed Nov. 1, 2005.
Notice of Allowance dated Mar. 10, 2008, U.S. Appl. No. 11/264,112, filed Nov. 1, 2005.
Notice of Allowance dated Dec. 2, 2008 in U.S. Appl. No. 11/931,092.
Office Action dated Nov. 17, 2010, U.S. Appl. No. 12/430,388.

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