Multiple data path simulator

Details Multiple data path simulator Multiple data path simulator

1984-12-24

1987-03-31

Atkinson, Charles E.

Excavating

324 73R, 371 23, 371 15, 371 28, G01R 3128

Patent

active

046548513

ABSTRACT:
A multiple data path simulator for use with a data generator having a clock output and a data output including a data delay with a predetermined number of outputs, a data multiplexer for selecting one of the outputs, a clock delay with a predetermined number of outputs corresponding to those of the data delay, a clock multiplexer for selecting one of the clock delay outputs and a gray code counter for determining which outputs are selected is disclosed. Multiplexers determine which outputs are main and which are standby. A second clock multiplexer is one time delay behind the first clock multiplexer and provides clock to the gray code counter when counting up. The gray code counter uses the output of the first clock multiplexer when counting down.

REFERENCES:
patent: 3027542 (1962-03-01), Silva
patent: 3047841 (1962-07-01), Kondi
patent: 3737637 (1973-06-01), Frankeny et al.
patent: 4497056 (1985-01-01), Sugamori
patent: 4564943 (1986-01-01), Collins et al.
patent: 4577318 (1986-03-01), Whitacre et al.

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