Boots – shoes – and leggings
Patent
1983-09-29
1989-01-24
Kemeny, Emanuel S.
Boots, shoes, and leggings
G06F 928
Patent
active
048004863
ABSTRACT:
The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent to clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.
REFERENCES:
patent: 3886523 (1975-05-01), Fergusen et al.
patent: 3900723 (1975-08-01), Bethany et al.
patent: 4041461 (1977-08-01), Kratz et al.
patent: 4101960 (1978-07-01), Stoves et al.
patent: 4112489 (1978-09-01), Wood
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 4179734 (1979-12-01), O'Leary
patent: 4179735 (1979-12-01), Lodi
patent: 4187539 (1980-02-01), Eaton
patent: 4202039 (1980-05-01), Epenay et al.
patent: 4214301 (1980-07-01), Kurihara et al.
patent: 4251885 (1981-02-01), Dodt et al.
patent: 4253183 (1981-02-01), Taylor et al.
patent: 4270181 (1981-05-01), Tanakina et al.
patent: 4315313 (1982-02-01), Armstrong et al.
patent: 4376976 (1983-03-01), Lahti et al.
patent: 4392200 (1983-07-01), Arulpragasam et al.
patent: 4414669 (1983-11-01), Heckelman et al.
patent: 4435765 (1984-03-01), Uchida et al.
patent: 4454578 (1984-06-01), Matsumoto et al.
patent: 4594655 (1986-06-01), Hao et al.
patent: 4617625 (1986-10-01), Nagashima et al.
patent: 4621324 (1986-11-01), Ushiro et al.
Ramcanoorthy and Li, Pipeline Architecture, 3/77, pp. 61-102, Computing Surveys, vol. 9, No. 1.
Siewiorek et al., Computer Structures: Principles and Examples, 1982, pp. 439-446.
Beirne John M.
Costantino Cirillo L.
Horst Robert W.
Lynch Shannon J.
Kemeny Emanuel S.
Lynt Christopher H.
Tandem Computers Incorporated
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