Multiple data clock activation with programmable delay for use i

Details Multiple data clock activation with programmable delay for use i Multiple data clock activation with programmable delay for use i

1998-08-17

2000-05-09

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Sync/clocking

365202, 365190, 365194, 365208, G11C 818

Patent

active

060612967

ABSTRACT:
A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.

REFERENCES:
patent: 5991227 (1999-11-01), Park
patent: 6005825 (1999-12-01), Lee et al.
patent: 6009040 (1999-12-01), Choi et al.

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