Multiple clock synthesizer

Details Multiple clock synthesizer Multiple clock synthesizer

1989-07-20

1991-08-13

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 377 77, 377 78, 328 63, 328 72, H03K 1700, H03K 513

Patent

active

050399500

ABSTRACT:
The synthesizer of the present invention is a multiple clock synthesizer for generating multiple clock signals with improved clock width and position accuracy. Within the synthesizer an oscillator provides a train of pulses corresponding to a base signal. A plurality of delay devices, formed of differing lengths of cables, are coupled to the oscillator with each cable providing a different delay to the train of pulses to in turn provide a plurality of delayed clocking signals. A plurality of registers, each having, a clocking input, a plurality of output taps, and load inputs and corresponding in number to the plurality of delay devices receive on their clocking inputs a delayed clocking signal from an associated one of the plurality of delay devices. A binary number is circulated in each of the plurality of registers as a function of the associated clocking signal to provide at their outputs a sequence of pulses each having a leading edge displacement defined by 1 divided by the number of outputs from the plurality of delay devices, times the number of outputs per register, times the element clock period. The number of outputs in the clock delay section corresponding to the number of register used.

REFERENCES:
patent: 4124898 (1978-11-01), Munter
patent: 4171517 (1979-10-01), Higa et al.
patent: 4328588 (1982-05-01), Smithson
patent: 4713623 (1987-12-01), Mower et al.

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