Multiple clock power down method and structure

Details Multiple clock power down method and structure Multiple clock power down method and structure

1984-07-27

1987-05-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200A, 307453, 307443, 307480, 365227, H03K 17687, H03K 19096, H03K 1920

Patent

active

046653287

ABSTRACT:
A method and structure is provided for powering down a plurality of clocks in a predetermined sequence. In one embodiment, a clock is powered down when it reaches a predefined logical level following the receipt of a power down signal. In another embodiment, a clock is powered down in response to a power down signal when the clock reaches a predefined level, and all clocks derived from that clock reach predefined levels. This is accomplished by including an edge sense circuit for determining when a clock reaches a predefined level, circuitry for combining a plurality of logical signals which indicate when the clock has reached said predefined level, and when all clocks derived from that clock have been powered down. Means and structure are also provided for powering down internal read/write control signals in response to a power down signal, thereby minimizing power consumption which would occur if the read/write control signals were switching during the power down cycle.

REFERENCES:
patent: 3745380 (1973-07-01), Kitajima et al.
patent: 4011468 (1977-03-01), Fosler, Jr. et al.

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