Multiple-clock controlled logic signal generating circuit

Details Multiple-clock controlled logic signal generating circuit Multiple-clock controlled logic signal generating circuit

2007-09-18

2007-09-18

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189080, C365S189120, C327S099000, C327S298000

Reexamination Certificate

active

11373461

ABSTRACT:
A multiple-clock controlled logic signal generating circuit is proposed, which is designed for use to generate a logic signal during specified periods with reference to multiple clock signals; and which is characterized by the use of a set of switching modules to switch between two different input signals and two different clock signals and the use of an S-R flip-flop unit to output either the first input signal or the second input signal during different specified periods. This feature allows the architecture of the proposed multiple-clock controlled logic signal generating circuit to be more simplified than prior art and thus easier to implement.

REFERENCES:
patent: 6441668 (2002-08-01), Miller
patent: 7057431 (2006-06-01), Kwak
patent: 2003/0133747 (2003-07-01), Chang

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