Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2003-02-21
2004-09-14
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000, C257S685000, C257S723000, C257S738000, C257S737000, C257S778000, C257S680000, C257S774000, C257S668000
Reexamination Certificate
active
06791192
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to packaging structures for integrated circuit chips and more particularly to control of functions thereof.
2. Description of Related Art
U.S. Pat. No. 5,789,303 of Leung et al., assigned to Northern Telecom Limited for “Method of Adding on Chip Capacitors to an Integrated Circuit” shows thin capacitors (
100
) and (
200
) deposited on the planarized surface of chips in
FIGS. 3 and 4
. The capacitor layers are formed by deposition, photolithographic masking, etching, and selective deposition as described at Col. 5, lines 17-50.
U.S. Pat. No. 5,814,871 of Furukawa et al assigned to Fujitsu, Ltd. for “Optical Semiconductor Assembly Having a Conductive Floating Pad” shows a chip capacitor (
44
) or (
46
) in FIG.
4
C. thereof formed on the surface of a “metal stem
6
” which carries a preamplifier IC (
28
).
U.S. Pat. No. 5,926,061 of Kawasaki assigned to Fujitsu, for “Power Supply Noise Eliminating Method and Semiconductor Device” shows what appears to be a planar on-chip capacitor C
2
on chip (
2
) in FIG.
24
and described at Col. 10, lines 19-34.
U.S. Pat. No. 5,963,110 of Ihara et al., assigned to Fujitsu, for “Equalizing Filter and Control Method for Signal Equalization” shows a chip capacitor C
2
T in
FIG. 14
bridging a pair of output patterns (P
1
) and (P
2
) and described at Col. 7, lines 26-39.
U.S. Pat. No. 4,598,307 of Wakabayashi et al. for “Integrated Circuit Device Having Package with Bypass Capacitor” shows a bypass capacitor mounted externally in an opening in a marginal area of the lid of a Integrated Circuit (IC) chip package, which is an Dual-In-Line (DIP) type package.
U.S. Pat. No. 5,475,262 of Wang et al. for “Functional Substrates for Packaging Semiconductor Chips” shows stacked multiple levels of interconnected substrates with a separate signal connection substrate, a separate capacitor substrate, a separate resistor substrate, and a separate power supply substrate. Confronting substrates have a plurality of bond pads which are interconnected by inter-substrate contacts between the substrates which may be deformable bumps or other electrical connectors or contacts selected from solder bumps, elastomer bumps and gold bumps.
U.S. Pat. No. 5,498,906 of Roane et al. for “Capacitive Coupling Configuration for an Integrated Circuit Package” shows an externally mounted bypass capacitor for a IC package.
U.S. Pat. No. 5,608,262 of Degani et al. for “Packaging Multi-Chip Modules without Wire-Bond Interconnection” describes at Col. 4, lines 8-11 “a silicon-on-silicon structure having a silicon substrate . . . provided with metallizations to which each chip or die . . . is interconnected in a flip-chip manner by means of solder . . . .”
U.S. Pat. No. 5,854,534 of Bilin et al. for “Controlled Impedance Interposer Substrate” shows an interposer which incorporates a bypass capacitor.
U.S. Pat. No. 5,898,223 of Frye et al. for “Chip-on-Chip Package” shows chip-on-chip packages using solder bump interchip connections as vias between a single level interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper chip using solder bumps to form connections between the confronting chips.
U.S. Pat. No. 5,939,782 of Malladi shows a “Package Construction for an Integrated Circuit Chip with a Bypass Capacitor” buried in a compartment defining an inner chamber in a multilayer substrate formed of a number of generally parallel insulating layers.
U.S. Pat. No. 5,818,748 of Bertin and Cronin for “Chip Function Separation onto Separate Stacked Chips” shows an chips stacked face to face connected together both physically and electrically by FSC's (Force responsive Self-interlocking microConnectors) including confronting pedestals on which FSC's are formed.
U.S. Pat. No. 5,977,640 of Bertin et al for “Highly Integrated Chip-on-Chip Packaging” shows a chip-on-chip component connection/interconnection for electrically connecting functional chips to external circuitry.
Takahashi et al. “3-Dimensional Memory Module”, Semi, pp. 166-167 (1997) shows a stack of flip chips on carriers processed starting with flip chip bonding to a carrier and followed by the steps of epoxy resin casting, polishing, bump formation for stacking, and stacking multiple carriers.
SUMMARY OF THE INVENTION
The invention teaches a methods of mounting discrete chips on a chip package or multi-chip package which may include a bypass capacitor.
An object of this invention is to provide flexibility of functions of multiple chip packages.
Another object of this invention is to provide a separate inventory of products with different functions.
Still another object of this invention is control circuit design in the single chip for example for function selection.
Another object of this invention is to pack a bypass capacitor in package or in combination chip package.
A problem solved by this invention is reduction of the inventory of several products with different functions.
Another object of this invention is to eliminate I/O noise.
A chip package for semiconductor chips is provided by the method of this invention.
In accordance with a first aspect of this invention a method of forming a chip package for a semiconductor chip include the following steps to provide a device in accordance with this invention. Form a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from (a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board. Form solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection. Preferably, provide a bypass capacitor with a first terminal and a second terminal, and connect the first terminal of the bypass capacitor to the power structure and connect the second terminal of the bypass capacitor to the ground structure. Juxtapose the capacitor and the power bus and the ground bus with the chip, and connect the first terminal to the power bus or power plane and connect the second terminal to the ground bus or ground plane. Alternatively, locate the capacitor on the opposite surface of the printed circuit board from the chip, and connect the first terminal to the power plane and connect the second terminal to the ground plane. Preferably, connect big solder balls to the opposite surface of the printed circuit board for interconnection thereof with another element.
In accordance with another aspect of this invention a method of forming a chip package for a semiconductor chip and the device produced thereby includes the following steps. Form a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board. Form a second printed circuit board having a top surface and a bottom surface. Bond a first chip to the top surface of the first printed circuit board and bond a second chip to the bottom surface of the first printed circuit board in a flip chip connection. Bond a third chip to the bottom surface of the second printed circuit board in a flip chip connection. Bond the chips to the printed circuit boards by means selected solder balls and gold bumps. Provide a bypass capacitor with a first terminal and a second terminal. Connect the first terminal of the bypass capacitor to the power plane. Connect the second terminal of the bypass capacitor to the ground plane. In an alternative feature, bond a fourth chip to the top surface of the second printed circuit board in a flip chip connection. Interconnect the bottom surface of the first printed circuit board and the top surface of the second printed circuit board with big solder balls. Preferably, bond a fourth chip to the second printed circuit board top surface. Provide a bypass capacitor with a first terminal and a second terminal. Connect the first terminal of the bypass capacitor to the power plane and connecting the second term
Lin Mou-Shiung
Peng Bryan
Ackerman Stephen B.
Jones II Graham S.
Megic Corporation
Saile George O.
Williams Alexander Oscar
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