Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2006-06-13
2006-06-13
Geyer, Scott (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S125000, C438S455000
Reexamination Certificate
active
07060529
ABSTRACT:
A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
REFERENCES:
patent: 5696404 (1997-12-01), Murari et al.
patent: 5739546 (1998-04-01), Saitou et al.
patent: 5770476 (1998-06-01), Stone
patent: 6055655 (2000-04-01), Momohara
patent: 6066886 (2000-05-01), Egawa
patent: 6121677 (2000-09-01), Song et al.
patent: 6157213 (2000-12-01), Voogel
patent: 6233184 (2001-05-01), Barth et al.
patent: 6262587 (2001-07-01), Whetsel
patent: 6365443 (2002-04-01), Hagiwara et al.
patent: 2001/0001502 (2001-05-01), Wong
patent: 2001/0042901 (2001-11-01), Maruyama
patent: 2001/0052635 (2001-12-01), Takayama
patent: 0 918 354 (1999-05-01), None
patent: 63-234553 (1988-09-01), None
patent: 01-220843 (1989-09-01), None
patent: 04-171860 (1992-06-01), None
patent: 06-13447 (1994-01-01), None
patent: 11-163062 (1999-06-01), None
Kiehl Oliver
Killian Mike
Mueller Gerhard
Reithinger Manfred
Stahl Ernst
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