Multiple chip processor architecture with reset intercept circui

Details Multiple chip processor architecture with reset intercept circui Multiple chip processor architecture with reset intercept circui

1995-05-19

1997-01-28

Shah, Alpesh M.

Boots, shoes, and leggings

3642323, 3642328, 3642329, 3642384, 364DIG1, G06F 1576

Patent

active

055985734

ABSTRACT:
An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals. A reset intercept circuit is provided on the non-volatile memory die for intercepting the signal which is provided to the reset input of the non-volatile memory die from external of the multi chip package. The reset intercept circuit provides a modified version thereof to the processor die. Particularly, the reset intercept circuit performs the function of sending a modified version of the reset signal to the processor die responsive to the present mode of operation of the multi chip package at the time the reset signal is received.

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