Multiple chip package semiconductor device

Details Multiple chip package semiconductor device Multiple chip package semiconductor device

2001-06-25

2003-04-08

Coleman, William David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C438S108000, C361S768000

Reexamination Certificate

active

06545366

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device using integrated circuits (IC) in which higher capacity, speed, and downsizing can be accomplished.
With a request of higher density packaging of semiconductor devices on a printed circuit board, a downsized semiconductor device sealed into a substantially semiconductor chip size that is called a chip scale package or chip size package (CSP) has been developed. In addition to the downsizing of a semiconductor device having one of such memory semiconductor devices or peripheral circuit semiconductor devices sealed therein (referred to as a single semiconductor device), a multi chip package (MCP) having a plurality of memory semiconductor chips sealed by a single sealing material has been developed for higher density packaging of semiconductor devices on a printed circuit board.
Regarding the method of sealing such a plurality of semiconductor chips with a single sealing material, horizontal arrangement of the chips makes the area occupied by the chips on the mounting substrate larger. For this reason, disclosed in JP, 11-204720, A are a stacked multi chip package (SMCP) having two semiconductor chips having peripheral electrode pads stacked one on the other with their main faces placed in the same direction, and another SMCP having two semiconductor chips having peripheral electrode pads stacked one on the other back to back with one main face placed upward and the other main face downward.
FIG. 9
shows a cross sectional view of a conventional SMCP having two semiconductor chips having peripheral electrode pads stacked one on the other with their main faces placed upward in the same direction.
FIG. 10
shows a cross sectional view of a conventional SMCP that has two semiconductor chips of the same outside dimension having peripheral electrode pads stacked back to back with one main face placed upward and the other main face downward.
FIG. 11
is a top plan view of a wiring substrate used for a conventional SMCP.
Referring to
FIG. 9
, a first semiconductor chip
1
having peripheral electrode pads
13
and a second semiconductor chip
2
smaller than the placement area of the peripheral pads
13
and having peripheral electrode pads
12
are fixed via a bonding layer
7
. The back face of the first semiconductor chip
1
is fixed to one side of an insulating substrate
3
having a wiring layer
4
formed thereon (front face), via a bonding layer
7
. The insulating substrate has the wiring layer
4
on one side. Using soldering paste, mounting bumps
10
are joined to lands
15
exposed from the back face of the insulating substrate
3
through through-holes
11
that are provided so as to correspond to the lands
15
arranged on the front face of the insulating substrate
3
.
Peripheral pads
13
and
12
on first and second semiconductor chips
1
and
2
, respectively, are electrically connected to fingers
14
via gold wires
8
using the ultrasonic thermocompression wire bonding method. All of the semiconductor chips
1
and
2
, the bonding layers
7
and gold wires
8
, and also predetermined face and portions of insulating substrate
3
and wiring layer
4
are sealed with resin.
FIG. 11
is a top plan view of a conventional insulating substrate
3
having a wiring layer
4
formed on only one side. The wiring layer
4
is composed of a successive pattern having fingers
14
, routing
16
and
17
, and lands
15
corresponding to one another. In this drawing, the fingers
14
are placed along the two sides of the peripheral areas of semiconductor chips
1
and
2
. The lands
15
are arranged in two central lines and in two lines each disposed outside of the two central lines at an equal pitch, i.e. in four lines in total, within the area in which the first semiconductor chip
1
is placed. Such an arrangement makes the routing
17
connecting the two central lines of the lands
15
and the corresponding fingers
14
longer than the routing
16
connecting the outside lines of the lands
15
and the corresponding fingers
14
. This causes a drawback of difference in their impedance.
When two conventional semiconductor chips
1
and
2
of the same outside dimension each having peripheral electrode pads
13
and
12
are stacked back to back with one main face placed upward and the other main face downward as shown in
FIG. 10
, the peripheral electrode pads must be placed in vertically inverted positions. The conventional SMCP has another drawback. Since metal bumps
6
of a diameter larger than the thickness of bonding material
7
are used for the connection between peripheral electrode pads
13
and corresponding fingers
14
, the SMCP becomes thicker by the size of bumps. In addition, since the SMCP is composed of semiconductor chips
1
and
2
having peripheral electrode pads
12
and
13
and a wiring substrate
3
shown
FIG. 11
, routing
17
connecting two central lines of lands
15
and corresponding fingers
14
is longer than routing
16
connecting two outside lines of lands
15
and corresponding fingers
14
. This causes another drawback of difference in their impedance on the wiring substrate.
As mentioned above, the conventional SMCP has a drawback that the semiconductor device placed on a mounting substrate has a larger thickness when mounted because semiconductor chips are stacked one on the other.
In addition, the conventional SMCP has another drawback. For example, two DRAM chips of the same dimension, each having a single line of electrodes or a plurality of lines of electrodes along the centerline of the semiconductor chip (referred to as a center pad arrangement semiconductor chip), are stacked one on the other so as to double memory capacity thereof. Such kind of SMCP cannot be constructed because wire bonding brings the wires into contact with the periphery of second semiconductor chip
2
(referred to as a chip edge short circuit).
Moreover, when a center pad arrangement semiconductor chip and a peripheral pad arrangement semiconductor chip of the same dimension are stacked one on the other, routing for connecting to the same lands
15
is more complicated and longer because of the inverted pads. This inhibited the accomplishment of higher speed, capability, and memory capacity.
SUMMARY OF THE INVENTION
The present invention addresses the above-mentioned problems. Therefore, the first object of the present invention is to provide a thin SMCP having two center pad arrangement semiconductor chips stacked one on the other so as to double memory capacity. The second object of the present invention is to reduce the difference in the impedance of routing between electrode pads and fingers by minimizing the difference in the length of routing between the electrode pads and fingers on the wiring substrate and using gold wires of high conductivity for connecting the center pads on each of the stacked chips and corresponding fingers.
A semiconductor device in accordance with a first aspect of the present invention has a wiring substrate having a through opening, and having lands, fingers, routing, and through holes on a first face and a second face thereof. A first semiconductor chip having center pads on the main face thereof is fixed to the wiring substrate on the second face thereof using bonding material so that the through opening surrounds the center pads. The back face of the first semiconductor chip and the back face of a second semiconductor chip are fixed to each other using bonding material. The pads on each semiconductor chip and corresponding fingers on the wiring substrate are connected via gold wires. The gold wires, each semiconductor chip, each bonding material, and the through opening are filled with sealing resin. In addition, the fingers on the first face in an area other than from land placement areas to peripheral areas are also sealed. Such a structure can make the entire thickness of the SMCP smaller.
The semiconductor device also has solder balls on the lands provided on the first face of the wiring substrate. Thus, mounting the device on a

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