Multiple-cell transistor with base and emitter fuse links

Electricity: electrical systems and devices – Safety and protection of systems and devices – Circuit interruption by thermal sensing

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Details

361103, H02H 504

Patent

active

047424257

DESCRIPTION:

BRIEF SUMMARY
PRIOR ART

The invention is based on a multiple-cell transistor consisting of parallel connections of individual transistor cells provided between respective base, emitter and collector bus bars and wherein a fuse path or link is connected in the collector-emitter paths and in the base connection of each transistor cell.
Such a multiple-cell transistor is already known from DE-PS No. 24 08 540. The multiple-cell transistor consists of a parallel connection of individual transistor cells between a common base, emitter and collector connection bar, by each instance, and is preferably constructed by integrated technology. The particular disadvantage of such a multiple-cell transistor consists in that the entire multiple-cell transistor is made inoperative when there is a short-circuit defect in a single transistor cell. Such defects can occur during production because of fabrication dispersion or due to impurities during manufacturing, but they can also be caused during operation by means of local thermal overloading or sudden over-voltage. The transistor cells which are defective because of production can be localized by means of subsequent individual measurement and can be separated from the composite structure by means of burning out the fuse segments of a connection. The transistor cells which become defective during the operation of the multiple-cell transistor, on the other hand, must be able to separate themselves so that a so-called self-healing effect is achieved.


ADVANTAGES OF THE INVENTION

The multiple-cell transistor, according to the invention, comprising voltage controlled switches connected between a connection bar and the connection point of a fuse link with the base connection, which is remote from the base, has the advantage that a particularly secure automatic separation of a defective transistor cell is achieved. Accordingly, it is possible to use broader structures for the base fuse link in integrated technology and to lower the requirements for finishing accuracy.
It is particularly simple to construct the voltage-disturbed switch by means of a single Zener diode which can be made in a particularly simple manner in integrated engineering by means of a transistor which is operated in the blocking direction and whose base and collector are connected to one another. A particularly advantageous switching characteristic of the voltage-controlled switch is achieved by means of using a thyristor. The latter can be activated by means of a Zener diode or by means of a voltage divider. In monolithic integrated engineering this thyristor can be produced in a particularly simple manner by means of connecting a p-n-p transistor with a n-p-n transistor.


DRAWING

Three embodiment examples of the invention are shown in the drawing and explained in more detail in the following description.
FIG. 1 shows the basic wiring of a multiple-cell transistor according to the invention;
FIG. 2 shows a circuit diagram of a transistor cell according to the first embodiment example;
FIG. 3 shows a transistor cell according to the second embodiment example;
FIG. 4 shows a circuit diagram of a transistor cell according to the third embodiment example;
FIG. 5 shows a top view of a transistor cell according to the first embodiment example;
FIG. 6 shows a view of a circuit diagram of a transistor cell according to the second embodiment example.


DESCRIPTION OF THE EMBODIMENT EXAMPLES

FIG. 1 shows an emitter bus bar 1, base bus bar 2 and collector bus bar 3 of a multiple-cell transistor, according to the invention, of which only a first transistor cell 41 and a second transistor cell 42 are shown in FIG. 1 for the sake of simplicity. Other transistor cells, which are not shown, are connected in parallel so that there is a lower power distribution to each individual transistor cell of the whole multiple-cell transistor.
The transistor cell 41 contains an output transistor 5 whose collector is connected to the collector bus bar 3 and whole emitter is connected to the emitter bus bar 1, via an emitter fuse link or segme

REFERENCES:
patent: 2925548 (1960-02-01), Scherer
patent: 3258704 (1966-06-01), Wittman
patent: 3509423 (1970-04-01), Czerny
patent: 3819986 (1974-06-01), Fukuoka
patent: 4325222 (1982-04-01), Nakamura et al.
patent: 4412265 (1983-10-01), Buuck
patent: 4562509 (1985-12-01), Lindgren
patent: 4686602 (1987-08-01), Bucksch

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