Patent
1997-07-17
1999-08-03
Sheikh, Ayaz R.
395308, 395293, G06F 1336, G06F 1338, G06F 1340
Patent
active
059336161
ABSTRACT:
A computer system is provided wherein a bus master generates a signal indicative of the type of cycle it plans to initiate when requesting bus ownership. Other bus masters may be configured to generate similar cycle-type signals. A bus arbiter samples each master's unique cycle type signal during the request phase, and further receives information regarding the status of various target resources. Based upon the cycle type signals from requesting masters and upon the target resource information, the bus arbiter determines whether a master is planning to access an unavailable target resource. A master that is planning to access an unavailable target resource will be denied access of the bus. Accordingly, other masters intending to initiate cycles to available target resources may be granted ownership of the bus. As a result, target termination retry cycles may be avoided, and bus bandwidth and overall system performance may be improved.
REFERENCES:
patent: 5548730 (1996-08-01), Young et al.
patent: 5555383 (1996-09-01), Elazar et al.
patent: 5619661 (1997-04-01), Crews et al.
patent: 5632021 (1997-05-01), Jennings et al.
patent: 5664122 (1997-09-01), Rabe et al.
patent: 5721839 (1998-02-01), Callison et al.
Lory Jay R.
Pecone Victor K.
Dell USA L.P.
Lefkowitz Sumati
Sheikh Ayaz R.
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