Multiple bus bridge system for maintaining a complete order by d

Details Multiple bus bridge system for maintaining a complete order by d Multiple bus bridge system for maintaining a complete order by d

1997-06-30

1999-04-13

Shin, Christopher B.

395309, 395877, 395868, 395733, G06F 1300

Patent

active

058945873

ABSTRACT:
A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY protocol. A bridge logic unit asserts an EMPTY signal when the secondary posting buffers are empty. Interrupt processing is delayed until the EMPTY signal is asserted thereby assuring that all writes are completed. If an interrupt is received and the EMPTY signal is not asserted then a DRAIN signal is asserted while the EMPTY signal is not asserted. The bridge retries all upstream write requests until EMPTY is asserted.

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