Multiple block transfer mechanism

Details Multiple block transfer mechanism Multiple block transfer mechanism

1994-09-09

1997-07-08

Eng, David Y.

Boots, shoes, and leggings

36494081, 3642408, G06F 1338

Patent

active

056470576

ABSTRACT:
A block data transfer system may comprise a microprocessor integrated within a bus controller, a bus, and a plurality of computer boards coupled together via the bus. A PAL (programmable array logic device), integrated within the bus controller, allows an efficient block transfer of data between components on the computer boards by asserting a binary signal to indicate to the bus controller when to continue the data transfer and when to truncate the data transfer. The PAL utilizes a counter, dependent upon the data transfer size, to control the binary indication signal. The binary signal overrides the architectural data transfer protocol, thereby eliminating "protocol overhead" timing associated in multiple data transfers by allowing the entire data block to transfer within one transfer protocol period.

REFERENCES:
patent: 4060849 (1977-11-01), Bienvenu
patent: 4198699 (1980-04-01), Caddell
patent: 4757446 (1988-07-01), Trottier
patent: 4797809 (1989-01-01), Sato
patent: 5237670 (1993-08-01), Wakerly

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