Multiple block mode operations in a frame buffer system designed

Details Multiple block mode operations in a frame buffer system designed Multiple block mode operations in a frame buffer system designed

1993-10-29

1996-07-02

Powell, Mark R.

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395162, 36523003, 36523008, 36518912, G06F 1200

Patent

active

055331874

ABSTRACT:
A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may be written to the array, and circuitry for writing to the memory cells a data representing a single pixel, for writing simultaneously to the memory cells data representing a number of pixels equal to the number of conductors on the data bus, or for writing simultaneously to the memory cells data representing an entire row of pixels of the array.

REFERENCES:
patent: 4648077 (1987-03-01), Pinkham et al.
patent: 4752893 (1988-06-01), Guttag et al.
patent: 4823302 (1989-04-01), Christopher
patent: 5046023 (1991-09-01), Katsura et al.
patent: 5282177 (1994-01-01), McLaury
patent: 5305278 (1994-04-01), Inoue

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