Multiple block memory with complementary data path

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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Details

C365S189050, C365S190000, C365S203000

Reexamination Certificate

active

11670632

ABSTRACT:
A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.

REFERENCES:
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 5337283 (1994-08-01), Ishikawa
patent: 5367488 (1994-11-01), An
patent: 5706229 (1998-01-01), Yabe et al.
patent: 6101145 (2000-08-01), Nicholes
patent: 6236619 (2001-05-01), Cho et al.
patent: 6462999 (2002-10-01), Amano

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