Multiple block memory with complementary data path

Details Multiple block memory with complementary data path Multiple block memory with complementary data path

2008-07-08

2008-07-08

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050, C365S190000, C365S203000

Reexamination Certificate

active

07397722

ABSTRACT:
A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.

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patent: 6236619 (2001-05-01), Cho et al.
patent: 6462999 (2002-10-01), Amano

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