Multiple block adder using carry increment adder

Details Multiple block adder using carry increment adder Multiple block adder using carry increment adder

2001-09-19

2004-12-14

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S714000

Reexamination Certificate

active

06832235

ABSTRACT:

FIELD OF INVENTION
This invention relates to an improved adder architecture in which both a carry increment adder is used with a carry lookahead adder.
BACKGROUND OF INVENTION
A conventional N-bit comprises adder building blocks. A common adder building block is a full adder that takes as input, bit A, bit B and carry-in bit Cin and produces sum S and carry-out Cout as illustrated in
FIG. 1. A
cascade of N full adders can be used to provide an N-bit ripple carry adder as illustrated in FIG.
2
.
FIG. 2
illustrates three adders adding three bits at input A (bits
0
-
2
) to three bits at input B (bits
0
-
2
) to get sum bits S
0
-S
2
) and carry (Cout). A ripple carry adder is one that the output sum gets updated from lower bits. The higher bit waits for the carry propagation from the lower bit adder. A ripple carry adder is too slow for most long adders since an n bit ripple carry takes N full delays.
The delay can be reduced by carry lookahead adder (CLA) that computes the carry through several bits using one complicated gate instead of a cascade of several full adders. An example of a 16-bit lookahead adder is illustrated in FIG.
3
. It has four 4-bit blocks
11
-
14
and the lookahead circuits
15
-
17
to quickly send the carry to the most significant bits at the ripple carry adder block
11
for summing bits
12
-
15
. Each of the blocks
11
-
14
includes four ripple carry full adders to sum four bits as illustrated with three bits in FIG.
2
.
A high speed adder can be provided using carry select adders (CSA). A 16-bit carry select adder (CSA) adder system comprises three 4-bit CSA adder blocks
22
-
24
and a 4-bit ripple carry adder block
21
is illustrated in FIG.
4
. The ripple carry block adder
21
adds the four least significant bits [
3
:
0
]. The most significant bit CSA adder block
24
adds the most significant bits [
15
:
12
], the next lower level bit CSA adder block
23
adds bits
8
-
11
([
11
:
8
]) and the lowest CSA adder block
22
adds bits
4
-
7
([
7
:
4
]). The block separation might be
4
-
4
-
4
-
4
as shown but may also be
5
-
4
-
4
-
3
or other. This depends on circuit optimization, input signal delays, etc. Each of the CSA adder blocks
22
-
24
comprises two ripple carry adders
25
and
26
to pre-compute carry- in “0” and “1” case. When carry-in is reached, the sum S output is “0” case or “1” case. The two short adders
25
and
26
at each block of four bits speculatively calculate the sum assuming the carry-in of a “0” or “1”, and the actual carry in to the trigger a multi-plexor (MUX)
27
selects the appropriate sum.
The CSA is one of the fastest adder architectures that realize high performance MAC unit, but it cannot generate carry signal as fast as CLA can. Since one of the most critical paths of the adder block is related to the generation of carry signal to the most significant bit (MSB), CLA circuit is used to generate carry signals sent to MSB.
A higher speed adder is a carry select adder (CSA) with carrier lookahead adder (CLA) circuits is illustrated in FIG.
5
. The example in
FIG. 5
is a 16-bit adder with a carry lookahead adder (CLA) circuit
28
between each 4-bit CSA adder
29
and between the ripple adder
29
a
and the CSA
29
b
with the CLA circuit used to generate carry signals to the MSB.
It is highly desirable to make this path faster without degradation of generation speed of the sum and thereby increase adder speed.
SUMMARY OF INVENTION
In accordance with one embodiment of the present invention an adder architecture is provided in which both carry lookahead and carry increment adders are used.
In accordance with another embodiment of the present invention a long adder is provided by the combination of carry select adder and carry increment adders.


REFERENCES:
patent: 4761760 (1988-08-01), Tomoji
patent: 5517440 (1996-05-01), Widigen et al.
patent: 5548546 (1996-08-01), Jang et al.
patent: 5898596 (1999-04-01), Ruetz
patent: 5912833 (1999-06-01), Jang et al.

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