Multiple bits-per-cell flash EEPROM memory cells with wide progr

Details Multiple bits-per-cell flash EEPROM memory cells with wide progr Multiple bits-per-cell flash EEPROM memory cells with wide progr

1997-05-09

1998-08-04

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518528, G11C 1604

Patent

active

057904561

ABSTRACT:
There is provided an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR memory architecture so as to eliminate program disturb during a programming operation. The array has a plurality of memory cells arranged in rows of word lines and columns of bit lines intersecting the rows of word lines. A programming current source is connected to the source of selected memory cells that are to be programmed in the corresponding columns of bit lines. A programming gate voltage is applied to control gates of the selected memory cells, and a programming drain voltage is applied simultaneously to the common array ground line connected to the drains of all of the memory cells. Further, a relatively low voltage is applied simultaneously to all of the control gates of non-selected memory cells in the array which are not to be programmed during the programming operation so as to eliminate the program disturb.

REFERENCES:
patent: 5245570 (1993-09-01), Fazio et al.
patent: 5555521 (1997-09-01), Hamada et al.
patent: 5625600 (1997-04-01), Hong
patent: 5638327 (1997-06-01), Dallabora et al.

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