Multiple bit multiplier

Details Multiple bit multiplier Multiple bit multiplier

1996-03-29

1998-07-28

Elmore, Reba I.

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G06F 700, G06F 1500

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057870284

ABSTRACT:
A finite field multiplier in GF2.sup.mn is formed from a pair of m celled shift registers and an m celled accumulating cell. Logical connections are established to generate grouped terms in respective cells of the accumulating cell upon retention of the vector of the subfield elements in each shift register. Each cell contains a subfield element in the form of an n-tuple and the logical connections perform arithmetic operations in accordance with the inherent subfield arithmetic to provide an n-tuple in each cell of the accumulating register. A product of two vectors can be obtained in m clock cycles. By mapping between registers, squaring of a vector can be obtained in one clock cycle.

REFERENCES:
patent: 4251875 (1981-02-01), Marver et al.
patent: 4587627 (1986-05-01), Omura et al.
patent: 4745568 (1988-05-01), Onyszchuk
patent: 4797848 (1989-01-01), Walby
Pincin, A New Algorithm for Multiplication in Finite Fields, IEEE Transactions on Computers, vol. 38, No. 7, pp. 1045-1049 (1989).

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