Multiple bit line memory architecture

Details Multiple bit line memory architecture Multiple bit line memory architecture

2000-10-31

2001-12-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000

Reexamination Certificate

active

06327169

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory architectures, and more specifically relates to a memory architecture which improves the performance of large memories.
BACKGROUND OF THE INVENTION
In a prior art memory architecture, memory cells are arranged in an array or matrix consisting of rows and columns. Each memory cell includes a pass transistor, and read/write word lines are connected to the pass transistors of the memory cells. Read/write bit lines are also connected to the memory cells, and the word lines are used to effectively connect the bit lines to the memory cells. Typically, the word lines are disposed horizontally through the rows of memory cells in the array, and the bit lines are disposed vertically through the columns of memory cells in the array. Each row of memory cells is connected to a single it word line, and each column of memory cells is connected to a single bit line. Therefore, each row of memory cells is associated with a different word line, and each column of memory cells is associated with a different bit line. Sense amplifiers are provided at the bottom of the array, and the bit lines are connected to the sense amplifiers.
This prior art arrangement is illustrated schematically in
FIG. 1
, wherein the dots
10
in the array represent memory cells, the horizontal lines represent word lines (wherein the array has n word lines), and the vertical lines represent bit lines (wherein the array has m word lines). As shown, each row of memory cells is associated with a different word line, and each column of memory cells is associated with a different bit line. Additionally, sense amplifiers
12
are provided at the bottom of the array, and each bit line is connected to a different sense amplifier. As shown, a decoder
14
is connected to the word lines, and an external device
16
is in communication with the decoder
14
. In operation, the external device
16
supplies a memory address to the decoder
14
, and the decoder
14
decodes the memory address and turns on a corresponding word line. The word line turns on pass transistors of the memory cells in the respective row of memory cells, and effectively connects the corresponding bit lines to the memory cells in the row.
The access time for a given memory cell is determined, at least in part, by how quickly the bit line which is connected to the memory cell is driven to the correct (i.e. threshold) voltage for the sense amplifier. Typically, the memory cells which are farthest from the sense amplifiers have the slowest access times due to loading on the bit lines.
To reduce access times, a prior art approach provides that a large memory array is effectively divided into a plurality of blocks. Such approach provides that each block has its own set of address decoders, sense amplifiers, column multiplexers (if the memory is implemented using multiple columns) and Input/Output (I/O) drivers, thus increasing the overall size of the memory.
OBJECTS AND SUMMARY
It is an object of an embodiment of the present invention to provide a memory architecture which improves the performance of large memories.
Another object of an embodiment of the present invention is to provide a memory architecture which provides reduced access times without having to increase the size of the memory.
Still another object of an embodiment of the present invention is to provide a memory architecture which provides that a large memory consumes less power.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a memory architecture which includes a plurality of memory cells arranged in rows and columns, a word line connected to each row of memory cells, and a plurality of bit lines connected to each column of memory cells.
Providing that more than one bit line is connected to each column of memory cells improves the performance of large memories, provides reduced access times without having to increase the size of the memory, and provides that a large memory consumes less power.
Preferably, a sense amplifier is connected to the bit lines. The bit lines may each be formed of the same material, or they may be formed of different material depending on the application. The memory cells may be disposed in a plurality of arrays, and the arrays may be symmetrical (i.e. where each array is the same size) or asymmetrical (i.e. where the arrays are not the same size).


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patent: 5396450 (1995-03-01), Takashima et al.
patent: 5555203 (1996-09-01), Shiratake et al.
patent: 5629987 (1997-05-01), Nakano et al.
patent: 5761109 (1998-06-01), Takashima et al.

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