Multiple-bit comparator with reliable output timing and reduced

Details Multiple-bit comparator with reliable output timing and reduced Multiple-bit comparator with reliable output timing and reduced

1997-03-20

1999-06-08

Wambach, Margaret R.

Communications: electrical

Digital comparator systems

G06F 702

Patent

active

059107626

ABSTRACT:
A multiple-bit comparator compares the individual bits of a first multiple-bit signal with the corresponding bits of a second multiple-bit signal. An output control circuit in the multiple-bit comparator detects, from transitions in the second signal, whether the second signal is valid or invalid, and holds an output signal at a fixed logic level when the second signal is invalid. When the second signal is valid, the output signal is controlled according to the combined results of the individual bit comparisons. The individual bit comparison results are preferably combined by wired-OR logic.

REFERENCES:
patent: 5281946 (1994-01-01), Van Le
patent: 5319348 (1994-06-01), Lee et al.
patent: 5534844 (1996-07-01), Norris
Jan. 20, 1988, pp. 108-109.
"Dynamic Comparator With Data Selftiming", 700 IBM Technical Disclosure Bulletin 38 (1995) No. 5, Armonk NY, USA; vol. 38, No. 05 May 1995, pp. 181-182.
"Comparison Circuit", IBM Technical Disclosure Bulletin (1980); vol. 23, No. 5; Oct. 1980; pp. 2032-2033.

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