Multiple biasing phase-lock-loops controlling center frequency o

Details Multiple biasing phase-lock-loops controlling center frequency o Multiple biasing phase-lock-loops controlling center frequency o

1993-04-28

1994-07-12

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 16, 331 17, 360 51, H03L 707

Patent

active

053292510

ABSTRACT:
A recovered clock signal is phase aligned with timing data that has been extracted by a digital signal processor (DSP) from an input signal by a multiple phase-lock-loop (PLL) clock recovery circuit that utilizes a digital error word generated by the DSP. The multiple PLL clock recovery circuit uses a first PLL and a second PLL to generate a first biasing signal and a second biasing signal, respectively, which have a magnitude which is a function of the frequency of a first clock signal and a second clock signal, respectively. A multiplexor allows either the first biasing signal or the second biasing signal to be selected as a selected bias signal. A controlled oscillator generates the recovered clock signal with a center frequency which is a function of the magnitude of a phase error signal. A digital-to-analog converter (DAC) generates the phase error signal by modifying the selected bias signal in response to the digital error word. The first biasing signal and the second biasing signal can be switched in and out of the DAC to quickly bias the DAC to drive the controlled oscillator to a specific center frequency.

REFERENCES:
patent: 4980652 (1990-12-01), Tarusawa et al.
patent: 5043677 (1991-08-01), Tomassetti et al.
patent: 5072195 (1991-12-01), Graham et al.
patent: 5075639 (1991-12-01), Taya
Goodenough, Frank, "DSP Technique Nearly Doubles Disk Capacity", Electronic Design, Feb. 4, 1993, pp. 53-58.
Llewellyn, William D., et al., A 33Mh/s Data Synchronizing Phase-Locked Loop Circuit (WAM1.1), presented at Session 1: High Speed Data Recovery, 1988 IEEE International Solid State Circuits Conference, Feb. 17, 1988, pp. 12, 13, 276, 277.
Gomez, Ray et al., An Analog Discrete-Time Processor for Magnetic Recording Channels, undated, from Integrated Circuits and Systems Laboratory, University of California, Los Angeles (4 pages) (no date).

Affiliated with

Also associated with

Rating

Multiple biasing phase-lock-loops controlling center frequency o does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple biasing phase-lock-loops controlling center frequency o, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple biasing phase-lock-loops controlling center frequency o will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-399525