Multiple bank simultaneous operation for a flash memory

Details Multiple bank simultaneous operation for a flash memory Multiple bank simultaneous operation for a flash memory

2000-03-15

2001-05-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185110, C365S185330, C365S230080

Reexamination Certificate

active

06240040

ABSTRACT:

BACKGROUND
The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to multiple bank simultaneous operation for a flash memory.
Flash memory (or flash RAM) is a form of non-volatile storage that uses a memory cell design with a floating gate. High voltages are applied to the memory cell inputs to program (store charge on) the floating gate or to erase (remove charge from) the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material, reducing the amount of electronic charge on the floating gate. Erasing a cell sets the logical value of the cell to “1” while programming the cell sets the logical value to “0”. Aside from programming or erasing operations, a flash memory operates similarly to a randomly accessible read only memory (ROM). Conventionally, a flash memory chip, including the flash memory storage cells and support logic/circuitry, is made by fabricating layers of semiconductor material and interconnect layers of polysilicon and first and second metal layers onto a substrate. It will be appreciated that there are numerous integrated circuit fabrication techniques, involving more or fewer layers, which are applicable herein.
This complex nature of programming and erasing flash memory devices leads to a major challenge in that such devices do not provide sufficiently fast write access which then affects read accesses. For example, conventional flash memory devices typically do not allow a processor to perform a read operation while a program or erase operation is underway in the flash memory device. In most implementations, the processor is required to periodically poll a status register of the flash memory device to detect the end of the program or erase operation before initiating a read operation to the flash memory device.
Unfortunately, as noted above, the programming and erase cycle times for typical flash memory devices are orders of magnitude greater than acceptable write access times of a conventional random access main memory using, for example, Dynamic Random Access Memory (“DRAM”). Such long latencies associated with programming or erase operations can lock up the operating system and prevent the system from finctioning for unacceptably long time intervals if the flash memory is the only memory in the electronic system. Some prior flash memories allow erase suspend operations in order to address this difficulty. Erase suspend allows the processor to pause an erase operation so another sector can be read. However, such memories typically still impose a suspend latency interval of several microseconds before a read operation can be initiated. A typical suspend latency interval is from 0.1 to 20 microseconds.
Prior systems may employ multiple flash memory devices in an attempt to prevent such operating system lock up. In such systems, the processor usually has read access to one of the flash memory devices while other flash memory devices are undergoing a program or erase operation. However, such systems typically suffer from high costs because multiple flash memory devices are implemented even though the capacity of a single flash memory device may accommodate the needs of the particular electronic device.
With conventional flash memories of the recent past, core cell data can not be read while other data are being programmed. From the system point of view, in order to program data into core cells of the flash memory, the microprocessor needs to issue a program command to the flash memory. Since the flash memory only is capable of reading out the data or programming the data individually or non-simultaneously, the program command has to be stored outside/external to the flash memory.
In addition, programming and erasing a flash memory involves higher than normal voltages as compared to performing read operations. The use of these higher than normal voltages present challenges when trying to implement the capability to simultaneously read while programming/erasing. Such challenges include difficulties in distributing the high voltages required for the program and erase operations along with normal voltage for read operations and handling increased noise induced on the read sense outputs by the use of high voltages elsewhere within the device. Further, depending on the implementation, redundant logic may also be employed which introduces further complexities.
In recent years, in order to address these issues, dual bank flash memories have been introduced. U.S. Pat. No. 5,867,430 to Chen et al., and U.S. Pat. No. 5,847,998 to Van Buskirk, et al., incorporated by reference herein, disclose dual bank architectures that enable simultaneous read and write operation. The dual bank flash memory can program the data while reading out other data (i.e. is capable of simultaneous operation), so the flash memory system can be greatly simplified.
Most recently, despite these advantages, dual bank flash memory systems have become more complex. Increasingly, design challenges have been encountered with respect to the addressing and data perspectives of flash memory implementation using multiple banks. It would be desirable to implement a more flexibly and efficiently designed flash memory, capable of multiple bank simultaneous operation. It would be advantageous to develop architecture and circuitry individualized and local to each bank so as to facilitate, for example, extension of the simultaneous operation architecture from dual bank or two banks to N banks.
Accordingly, there is a need for an extendable and flexible multiple bank architecture that is capable of simultaneous operation, that is, that allows simultaneous read and write (program or erase) operations.
SUMMARY
By way of introduction only, an exemplary embodiment of a multiple bank simultaneous read and write operation flash memory is presented.
An embodiment of an address buffering and decoding architecture to facilitate simultaneous reading from and writing to N banks of core memory cells in a memory is presented. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-
1
banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-
1
banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals. The address buffer circuitry is used to simultaneously provide a write address and a read address in order to access core memory cells. Respective first portions of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals. Respective second portions of the write and read addresses are provided to the respective address selection circuit.
Also presented is an embodiment of an N-tuple bank simultaneous operation flash memory. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-
1
banks. For the duration of a write operation at the Nth bank, a read operation can only be performed on any one of the other N-
1
banks. The memory includes a control logic circuit, address buffer circuitry, and N localized bank circuitries. The control logic circuit is used to generate N read select signals and N write select signals. The circuitries
1
through N-
1
of the N localized bank circuitries includ

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