Multiple array memory device with staggered read/write for high

Details Multiple array memory device with staggered read/write for high Multiple array memory device with staggered read/write for high

1992-08-06

1994-04-19

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518905, 36523003, 36523008, 365239, G11C 800

Patent

active

053052811

ABSTRACT:
A multiple array memory device formed on a single IC chip performing transfers of a series of data between the device and its interface at high speed. The device includes a memory having a plurality of groups of memory arrays. In a read operation, the device internally reads data from sequential locations starting at any desired address and extending across the memory arrays into a latch. As the data are output to the interface from the latch, sequential data from an adjacent group of array in the memory are internally read into the latch. Thus, a series of data can be output to the interface at high speed. The write operation is performed in a similar manner.

REFERENCES:
patent: 4646272 (1987-02-01), Takasugi
patent: 4802132 (1989-01-01), Ohsawa
patent: 4817054 (1989-03-01), Banerjee et al.
patent: 4849937 (1989-07-01), Yoshimoto
patent: 4855959 (1989-08-01), Kobayashi
patent: 5136546 (1992-08-01), Fukuda et al.

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