Multiple array high performance programmable logic device family

Details Multiple array high performance programmable logic device family Multiple array high performance programmable logic device family

1990-03-07

1991-05-14

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

364716, 34082583, H03K 19177, H03K 19092

Patent

active

050158848

ABSTRACT:
A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O marcrocells decouple the logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.

REFERENCES:
patent: 4758747 (1988-07-01), Young et al.
patent: 4876640 (1989-10-01), Shankar et al.
patent: 4903223 (1990-02-01), Norman et al.

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