Multiple array architecture for analog or multi-bit-cell memory

Details Multiple array architecture for analog or multi-bit-cell memory Multiple array architecture for analog or multi-bit-cell memory

1997-07-07

1999-04-20

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

365 63, 36523006, G11C 800

Patent

active

058963405

ABSTRACT:
A memory architecture divides memory cells of a memory into multiple memory arrays where each memory array has local row and column lines that are directly coupled to memory cells in the memory array and electrically isolated from other arrays. Continuous global row and column lines cross the memory arrays. The memory additionally includes global decoders that apply operating voltages to the global lines corresponding to a selected memory cell being access. Local decoders decode bits from the address signal to select an array containing the selected memory cell and connect the global lines to the selected memory array. Other memory arrays are disconnected from the global lines to avoid disturbance that would result from the operating voltage being applied to unselected memory cells. Alternative, embodiments include a memory including a row of memory arrays, or a column of memory arrays, or multiple rows and multiple columns of memory arrays. Another alternative embodiment has continuous global column, row, and source lines and local source lines. Global decoding circuitry applies a source bias voltage to the global source lines which local source decoders apply to the local source lines for unselected sectors in the array containing the selected memory cell. The source bias voltage reduces threshold voltage disturbances caused by programming voltage being applied to row lines.

REFERENCES:
patent: 5428568 (1995-06-01), Kobayashi et al.
patent: 5521864 (1996-05-01), Kobayashi et al.
patent: 5646886 (1997-07-01), Brahmbhatt
patent: 5706243 (1998-01-01), Mori
patent: 5708620 (1998-01-01), Jeong

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