Pulse or digital communications – Synchronizers
Reexamination Certificate
2000-01-04
2003-12-09
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Synchronizers
C375S356000, C375S226000
Reexamination Certificate
active
06661860
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to digital circuits and more particularly to systems and techniques to measure the time difference between arrival of two digital signal edges at a particular terminal or port of a circuit.
BACKGROUND OF THE INVENTION
In digital applications, much of the design process involves finding means to satisfy desired timing constraints between various clock and data signals. Deviation from an ideal, i.e. perfectly periodic, fully in-phase, clock over a chip degrades the achievable performance of a design because such clock imperfection requires that either the system clock runs slower, or extra logic is added to ensure correct performance. In particular, uncertainty or inconsistency in the instantaneous period of a digital clock, or spatial variation in the arrival time of corresponding edges of a clock must be characterized in order to optimize the design of such systems as large microprocessors, or digital signal processing chips. While off-chip methods exist to measure the average performance of a digital clock, the instantaneous worst-case behavior of the clock constrains the design, and that cannot be measured by looking at averaged waveforms using, for example, electron beam analysis, or photonic emission methods. Very precise timing information could also help characterize and debug radio communications signals where data is encoded in phase variations of a carrier signal.
As is known in the art, an arbiter circuit, or simply an arbiter, is a digital circuit used to indicate which of two signals arrives first (i.e., the voltage of which signal transitions from a logic ‘0’ to a logic ‘1’ first) at a particular point. It should be appreciated that the electrical characteristics of one arbiter as compared to another arbiter will vary due to differences in manufacturing tolerances, which cause the arbiter to be biased towards one input signal rather than another. It is conventionally assumed that the arbiter does not give a consistently correct output if the temporal difference between the rising transitions of the arbiter's two input signals is smaller than a certain minimum. This minimum time is called a “decision window,” and is now typically 50 picoseconds.
It would be desirable to provide a circuit or technique to determine which of a pair of signals arrives first at a given point in a system to better than 10 picosecond resolution; and further to measure the temporal difference between pairs of signals with precision better than 10 picoseconds. Such a circuit or technique would enable more precise and accurate characterization of digital clocks, and hence higher performance of digital systems, and furthermore may be useful in debugging and testing radio frequency communications systems.
SUMMARY OF THE INVENTION
In accordance with the present invention, a digital circuit includes a plurality of arbiters, each arbiter having first and second input ports and an output port providing an output signal. Each first input of the plurality of arbiters is connected to a first common line and each second input of the plurality of arbiters is connected to a second common line. The output signal of each arbiter will transition to a first state if a first input signal is high and a second input signal is low. The digital circuit further includes a decision circuit, having a plurality of inputs and an output. Each of the inputs of the decision circuit is connected to a corresponding output of one of the plurality of arbiters. The decision circuit output provides a signal indicative of the time difference between a signal fed to the first common line and a signal fed to the second common line. With such an arrangement, the difference in arrival times can be measured between digital signal edges of two pulses, which can be used to measure jitter or debugging communication systems.
In accordance with a further aspect of the present invention, the digital circuit further includes a plurality of bias circuits, each bias circuit providing a bias signal or a bias characteristic to a corresponding one of the plurality of the arbiters. The bias circuit provides each arbiter with an offset such that the arbiter acts as if one input were delayed. With such an arrangement, cross-over times among different arbiters can be varied.
In accordance with a still further aspect of the invention, a method for determining the electrical characteristics of the arbiters involves the steps of providing one digital signal on a first common input to a set of arbiters, and another digital signal on a second common input of the set of arbiters, and then deducing from resulting outputs of the arbiters and the known statistics of the input signals, electrical characteristics of the individual arbiters.
In accordance with a still further aspect of the present invention, a method for indicating the time difference between respective edges of two digital signal pulses includes the steps of providing a first digital signal to a first input of each of a plurality of arbiters and providing a second digital signal to a second input of each of the plurality of arbiters. The method further includes the steps of providing an output signal from each arbiter with the signal level of the output signal of each arbiter dependent upon the determination by the arbiter of which of the first and second input digital signals arrive first at the arbiter and providing each of the arbiter output signals to a decision circuit which uses the arbiter output signals to determine the difference in arrival times between each edge of the first and second input digital signals. With such a technique, a digital circuit is provided that can be used to measure phase jitter with higher precision than prior art techniques.
In accordance with a further aspect of the present invention, the method comprises selecting a plurality of arbiters having different transition or crossover points which transition at different instances in time with like input signals. With such a technique, phase jitter can be measured with greater than 10 picoseconds precision and as high as two picoseconds precision.
REFERENCES:
patent: 3737766 (1973-06-01), Lubarsky, Jr.
patent: 3820022 (1974-06-01), Watt
patent: 4412299 (1983-10-01), Huffman
patent: 4654586 (1987-03-01), Evans, Jr. et al.
patent: 4819080 (1989-04-01), Cucchietti et al.
patent: 4975634 (1990-12-01), Shohet
patent: 4998027 (1991-03-01), Mihara et al.
patent: 5610543 (1997-03-01), Chang et al.
patent: 5778217 (1998-07-01), Kao
patent: 5825211 (1998-10-01), Smith et al.
patent: 5844436 (1998-12-01), Altmann
patent: 6556583 (2003-04-01), Hayashi et al.
Vadim Gutnik et al., “On-Chip time measurement,” Symposium on VLSI Circuit Digest of Technical Papers, 2000, pp. 52-53.
Chandrakasan Anantha
Gutnik Vadim
Bocure Tesfaldet
Daly, Crowley & Mofford LLP
Massachusetts Institute of Technology
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