Multiple analog to digital converter clock phase alignment...

Details Multiple analog to digital converter clock phase alignment... Multiple analog to digital converter clock phase alignment...

2000-04-21

2001-03-20

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S131000, C341S122000

Reexamination Certificate

active

06204784

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to analog to digital converter circuits, and more particularly to techniques for ensuring accurate clock timing over wide temperature ranges.
BACKGROUND OF THE INVENTION
The timing alignment of the sampling clock that is used by each analog to digital converter is important for good image rejection of the interleaved output of multiple analog to digital converters. Clock phase alignment has typically been accomplished using fixed low value capacitors, solder pad jumper matrices on printed wiring boards, matched length cabling, fixed element passive delay lines, or active integrated circuits (programmable delay lines). These techniques suffer from one of the following disadvantages: lack of a means for temperature compensation or of a simple adjustment of the delay value, degradation of the clock phase jitter value, or insufficient adjustment resolution.
It would therefore be an advantage to provide a technique for improved clock alignment resolution.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, an analog to digital converter system with clock timing compensation is described. The system includes an analog to digital converter circuit having an input terminal for receiving an analog signal to be sampled and converted to a digital value, one or more output terminals providing one or more logical output signals, and a clock terminal for receiving a sampling clock signal for clocking the sampling of the input signal. A thermally compensated clock circuit is responsive to a clock signal for providing the sampling clock signal, and includes a low pass filter circuit comprising a resistor element and a varactor diode, and a varactor bias network for providing a thermally compensated varactor bias voltage to the varactor diode.
According to another aspect of the invention, varactor diodes are used in a low pass filter configuration to provide very fine resolution adjustments to the individual clock circuits in a multiple analog to digital converter circuit system. A thermally compensated varactor bias network allows the clock timing to stay within specification over a wide temperature range.


REFERENCES:
patent: 5488369 (1996-01-01), Miller
patent: 5563596 (1996-10-01), Snyder et al.
Data Sheet for Analog Devices A/D Converter AD9070 (16 Pages).

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