Electricity: power supply or regulation systems – In shunt with source or load – Using choke and switch across source
Reexamination Certificate
2003-04-03
2004-10-12
Vu, Bao Q. (Department: 2838)
Electricity: power supply or regulation systems
In shunt with source or load
Using choke and switch across source
C323S284000, C323S285000
Reexamination Certificate
active
06803750
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates to improvements in multi-phase synchronous buck converters, and in particular, to such devices having improved techniques for output current sensing, for current sharing between modules, and improved transient performance during rapid load changes. The invention is described and shown in the context of a multi-chip module (MCM) implementation, but the improvements disclosed are applicable to discrete component implementations as well.
2. Relevant Art
An MCM is an electronic package which includes multiple integrated circuits (ICs) formed on a common substrate with multiple interconnecting layers, separated by insulating material. The entire module is encapsulated, but not the individual ICs.
MCMs offer several important benefits over circuits formed of separate chips mounted on conventional printed circuit boards. These include increased wiring and component densities, and lower cost. Also, the compact architecture of MCMs can result in shorter signal transmission times and reduced parasitic impedance, which in turn, improves high-speed switching efficiency. Also, including passive components inside MCM makes the MCM more testable as a complete power supply with consequent improved reliability.
MCM packaging is suitable for a wide variety of applications, including multi-phase synchronous buck converters. A synchronous buck converter is a switched D.C. power supply which receives a D.C. (or a rectified A.C.) input and produces a regulated low-voltage output with high output current capacity. Buck converters are particularly useful as power supplies for microprocessor operated devices, and a wide range of other digital circuit applications.
The basic configuration of a synchronous buck converter is illustrated in FIG.
1
. The circuit, generally denoted at
100
, includes a series switch
102
which is typically a power MOSFET or the like, with its source-drain path connected between an input terminal
104
and a first signal node
106
, a shunt switch
108
, also typically a power MOSFET or the like, and an output circuit comprised of an series inductor
112
and a shunt capacitor
114
connected to inductor
112
at a signal output node
116
and to ground
110
. A shunt diode such a Shottky diode
118
may also be provided in parallel with MOSFET
108
if desired to provide conduction during the deadtimes of
108
to reduce the diode reverse recovery loss associated with the internal body diode of MOSFET
108
. A separate diode
118
is not required if the higher switching loss is deemed preferable to the added cost of the external Schottky.
A D.C. input voltage V
IN
is provided between input terminal
104
and ground
110
across an input capacitor
111
, and an output voltage V
OUT
which is less than V
IN
is provided to a load
124
connected between signal output node
116
and ground
110
.
Control of the output voltage is provided by selectively varying the on-off duty cycles of MOSFETS
102
and
108
. This is done by a gate control logic or driver circuit
120
connected to the gate terminals of the MOSFETS, and driven by a pulse width modulation circuit
124
comprised of a PWM generator
124
which compares a ramp signal of the required switching frequency and having fixed maximum (peak) and minimum (valley) values with a signal provided by an error amplifier
126
. The latter provides an output signal V
E
based on the difference between the actual output voltage represented by a feedback signal V
FB
on signal line
128
and a desired output voltage signal V
REF
provided at a second input terminal
130
.
In operation, with MOSFET
102
on and MOSFET
108
off, the voltage across inductor
112
is equal to V
IN
−V
OUT
and the resulting current charges capacitor
114
. To maintain substantially constant voltage across capacitor
114
, a predetermined value of V
E
operates PWM circuit
124
and gate driver
120
to switch MOSFET
102
off, and MOSFET
108
on. The very low source-drain resistance of MOSFET
108
when it is conducting maintains a circuit to sustain the current flow through inductor
112
. This, in turn, allows capacitor
114
to charge, and after several on-off cycles for the MOSFETS, a steady-state output voltage is achieved. The operation of the circuit shown in
FIG. 1
is well known to persons skilled in the art, and a further description will be omitted in the interest of brevity.
Where output currents exceeding the capacity of MOSFETS
102
and
108
are required, a multi-phase buck converter can be employed, as illustrated schematically by circuit
200
shown in FIG.
2
. Here, N synchronous buck converters stages
202
A-
202
N are connected between an input node
108
and a common ground
210
and with their outputs feeding an output node
212
. Thus, each stage contributes a portion of the required current demand.
Converter stage
202
A includes an input capacitor
203
, a MOSFET pair
204
, an a shunt Shottky diode
205
, an output inductor
206
, an output capacitor
214
, and a gate drive circuit
216
. The other converter stages are similarly constructed.
A master PWM controller
218
generates N interleaved or out of phase PWM signals with 360°/N phase delay between phases. Master controller
218
may be constructed in any suitable or desired manner, and may be comprised, for example, of an adjustable frequency master clock
220
operating at a frequency F
M
=N·f
SW
, where N is the number of phases, and f
SW
is the predetermined switching frequency for the MOSFETS, a programmable counter
222
to generate a pulse train at frequency f
SW
, a succession of N series-connected PWM circuits
224
A-
224
N, and an error amplifier
226
. The latter provides a common input to trigger the PWN circuits whereby a series of drive signals PWM-1 through PWM-N are provided as inputs to gate driver
206
in converter stages
202
A-
202
N.
The drive signals are separated by a phase delay of 360/N, as shown in
FIG. 3
, which illustrates the timing of the synchronization signals for a five-phase converter with a 5 MHz clock frequency, and a 1 MHz switching frequency. From this, it will be seen that the five converter stages operate in a staggered fashion during five successive 1 MHz switching cycles, each interleaved by (⅕)* 10
−6
sec. As multi-phase synchronous buck converters are well known to those skilled in the art, further details concerning the arrangement shown in
FIG. 2
are omitted (as in the case of
FIG. 1
) in the interest of brevity.
There are, however, certain respects in which further improvements to existing designs for synchronous buck converters would be desirable. Among these are:
(a) Improved ways of generating the current feedback signal for input to the PWM controller. The output voltage and the current sharing in the individual converter stages of a multi-phase converter are controlled by the switching duty cycle for the MOSFETS. Since high output currents favor “lossless” type sensing, the current feedback signal is conventionally generated by a sample and hold circuit
400
such as illustrated in FIG.
4
. Here, the voltage across the R
DS-ON
of shunt MOSFET
402
is sampled once during each MOSFET switching cycle. Sample and hold circuit
400
includes transistors
404
and
406
(shown for simplicity as on-off switches) and a capacitor
408
.
Alternatively, if the V
IN
to V
OUT
ratio is such that the series FET has large duty cycle, the voltage across the R
DS-ON
of the series MOSFET rather than the shunt MOSFET can be sampled.
Either way, however, due the small value typical of R
DS-ON
, however, the sampled voltage signal must be amplified by amplifier
410
.
There are several drawbacks to this approach. For one thing, amplifier
410
needs to have a high bandwidth and high slew rate to accurately sample the voltage across the R
DS-ON
of shunt MOSFET
402
. Also, the output of amplifier
410
takes time to settle which limits its high frequency response. Further, there is inherently a large current ripp
International Rectifier Corporation
Ostrolenk Faber Gerb & Soffen, LLP
Vu Bao Q.
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