Multiphase level shift system

Details Multiphase level shift system Multiphase level shift system

2007-06-15

2010-10-05

Tan, Vibol (Department: 2819)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S299000, C327S115000, C327S258000, C327S251000, C331S057000, C331S051000

Reexamination Certificate

active

07808295

ABSTRACT:
Each of n level shifters (LS0to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0to LS7) are equal to each other.

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