Multiphase, interleaved direct digital synthesis methods and...

Details Multiphase, interleaved direct digital synthesis methods and... Multiphase, interleaved direct digital synthesis methods and...

2000-06-27

2003-07-01

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S270000

Reexamination Certificate

active

06587863

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to direct digital synthesis.
2. Description of the Related Art
Direct digital synthesis (DDS) utilizes digital processing to generate output signals whose stability is referenced to a precision clock and whose frequency and phase are tunable. An exemplary conventional DDS generator
20
is shown in FIG.
1
A. It includes a phase accumulator
22
and a phase-to-amplitude (&phgr;-A) converter
24
that both receive a clock signal f
clk
from a system clock
25
.
The phase accumulator
22
is basically a modulo &phgr;
s
digital N-bit counter that counts at a rate f
clk
wherein &phgr;
s
is a phase step that is provided to the phase accumulator at a generator port
26
. Accordingly, the phase accumulator delivers a periodic stream of digital works over a circuit path
27
to the &phgr;-A converter
24
.
This operation can be illustrated with reference to a digital phase wheel
30
of FIG.
1
B. As exemplified by successive radial rays
31
A,
31
B,
31
C,
31
D and
31
E in this wheel, the phase accumulator repetitively counts around the wheel perimeter
32
(e.g., from an initial N-bit digital word 0000 . . . 0 to a final N-bit digital word 1111 . . . 1) to form the periodic stream of digital words. As further indicated in association with a process direction arrow
33
, the N-bit phase accumulator
22
of
FIG. 1A
has a word capacity C=2
N
so that it generates a periodic stream of digital words over the circuit path
27
with a period P=C/(&phgr;
s
f
clk
). Stated differently, the phase accumulator
22
places digital words on the circuit path
27
at a rate of f
clk
and the periodic stream of words repeats at an output frequency of f
out
=(&phgr;
s
f
clk
)/C.
FIG. 1B
appears to indicate that the phase step &phgr;
s
moves only between adjacent digital words
34
. It should be understood, however, that
FIG. 1B
would need to show 268,435,456 digital words along its perimeter
32
to completely illustrate the operation of an exemplary 28-bit phase accumulator. Because of illustrative limits, such word density cannot be shown in the figures and, accordingly, the enlarged view of
FIG. 1C
indicates that additional words
36
may be located between each adjacent pair of the words
34
of FIG.
1
B—the number of the additional words being a function of the size of the selected phase step &phgr;
s
.
The periodic stream of digital words on the circuit path
27
of
FIG. 1A
includes a repetitive sequence from 000 . . . 0 to 111 . . . 1. This sequence expresses a linear relationship and, accordingly, a periodic analog ramp would be generated if the periodic stream were fed directly to a digital-to-analog converter (DAC). Therefore, the DDS generator
20
includes a &phgr;-A converter
24
which converts the digital words at respective phase locations to converted digital words at the generator output port
28
wherein the converted digital words represent respective amplitudes of any predetermined waveform (e.g., a sinusoidal waveform). A DDS synthesizer may then be realized by coupling a DAC to the generator output port
28
.
When compared to other waveform synthesis techniques (e.g., phase-locked loop synthesis), DDS offers a number of attractive features which include:
a) extremely fine tuning resolution of the output frequency f
out
,
b) fast change of output phase and fast phase-continuous change of output frequency f
out
;
c) generation of multiple phase-related periodic streams,
d) performance that is not affected by component changes (due, for example, to aging and temperature),
e) remote control (e.g., by digital processors), and
f) integrated structure on a single chip (including an output DAC).
It is apparent that the output frequency f
out
of the DDS generator
20
can only be increased with a corresponding increase in the rate f
clk
at which the phase accumulator
22
and &phgr;-A converter
24
operate. This rate, however, is limited by the DDS generator's fabrication process. Complementary metal-oxide semiconductor (CMOS) processes, for example, are characterized by the minimum gate length (e.g., 0.25 microns) they can achieve and this gate length sets an upper bound on the operating rate of devices fabricated with the process.
In addition to this absolute limit, attempts to increase the operating rate f
clk
face other problems such as higher current slew rates, tighter timing requirements and the need for more extensive signal pipelining. As a result, circuit complexity and power dissipation are increased and larger device geometries are required. It is apparent, therefore, that substantial benefits would be realized with methods and structures that increased DDS output frequencies f
out
without requiring a corresponding increase in the operating rate f
clk
.
SUMMARY OF THE INVENTION
The present invention is directed to DDS methods and structures that increase DDS output frequencies f
out
without requiring a corresponding increase in the rate f
clk
at which DDS structures must operate.
An exemplary method of the invention generates a periodic stream of digital words at a clock frequency f
clk
wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step &phgr;
s
. The method comprises the steps of:
a) with a count capacity C, counting modulo n&phgr;
s
at a reduced clock frequency (1
)f
clk
to thereby generate a primary substream of digital words;
b) phase offsetting the primary substream to form n−1 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step &phgr;
s
;
c) converting the digital words of each of the primary and secondary substreams to converted digital words that represent respective amplitudes of the predetermined waveform; and
d) interleaving the primary and secondary substreams to thereby form the periodic stream of digital words that occur at the clock frequency f
clk
.
These process steps can be practiced with any integer n and they form a multiphase, interleaved method that generates a periodic stream of digital words that occur at a clock frequency f
clk
but realizes this stream with counting, offsetting and converting processes that are realized at a substantially reduced frequency (1
)f
clk
. Therefore, significant improvements in DDS operational parameters (e.g., decrease of current slew rates, decrease of data pipelining, reduced circuit complexity and power dissipation and smaller device geometries) are realized.
DDS generator and synthesizer embodiments are also provided for practicing the methods of the invention.


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Amir Sodagar et al., aplitude Conversion in Sine-Output Direct Digital Frequency Synthesizers, 2000, IEEE, pp. 515-518.*
Stane Ciglarie et al., Special Considerations for Alternatively Designed Digital Phase Angle Standard, 1998, IEEE Transactions on Instrumentation and Measurement vol. 47 No. 1, pp. 199-203.*
Synthesizer Data Book,pp. 39-48 and 83-88, Qualcom Incorporated, San Diego, California, 92121.

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