Multiphase comparator

Details Multiphase comparator Multiphase comparator

2002-08-14

2004-01-27

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000, C327S065000, C327S089000

Reexamination Certificate

active

06683479

ABSTRACT:

FIELD OF INVENTION
The invention relates to a multiphase comparator circuit.
RELATED APPLICATIONS
This application claims the benefit of the Nov. 20, 2001 priority date of German application 101 56 817.7, the contents of which are herein incorporated by reference.
BACKGROUND
A typical comparator topology of a known comparator is illustrated in FIG.
1
. This comparator comprises a current source M
1
, which is alternately connected in each case to one of two differential stages
2
,
4
via a switching arrangement M
2
A, M
2
B. The first differential stage
2
comprises the transistors M
3
A, M
3
B and serves for amplifying a differential signal present at the signal inputs IM, IP in a first clock phase. The amplified differential signal present at the nodes A, B is finally amplified further in a second clock phase by means of the second differential stage
4
, which comprises the transistors M
4
A, M
4
B.
The clock phases are prescribed by the switching arrangement
3
with the transistors M
2
A, M
2
B. The clock signals are CLK=1, CLKB=0 in the first clock phase and CLK=0, CLKB=1 in the second clock phase.
The first clock phase is often referred to as “sampling phase” in the literature, and the second clock phase as “regeneration phase.” Accordingly, the second differential stage is often also referred to as regeneration stage.
At their output A, B, the differential stages
2
,
4
are connected to a common load element
5
. The load element
5
may comprise two resistors, for example, as is shown in
FIG. 1
a
. In the case of the present CMOS realization of a comparator, it is possible to provide the load element
5
with PMOS transistors which operate in the triode region, as is illustrated in FIG.
1
. In this case, a suitable potential for setting this operating point is fed to the gate terminals of the PMOS transistors.
In
FIG. 1
c
, the load element
5
comprises cross-coupled PMOS transistors. Further variants, such as e.g. a parallel circuit of
FIG. 1
a
and
FIG. 1
b
, are likewise conceivable as load element
5
.
The disadvantage of this comparator topology is that, at relatively high clock frequencies, in particular a number of GHz, the bit error rate rises greatly because the time for the regeneration process, in which the regeneration stage amplifies further the small differential signal present between the nodes A and B, becomes ever shorter as the frequency rises. Even with optimized dimensioning of the switching elements, a fundamental speed limit results from the regeneration time constant &tgr;
τ
~
C
g
m
where C is the capacitance at one of the nodes A, B of the comparator and g
m
is the transconductance of the transistors M
4
A, M
4
B of the regeneration stage
4
.
The regeneration time constant &tgr; as such can be understood as a technological constant of a given semiconductor fabrication process. Although the minimum regeneration time constant can be achieved by optimum circuitry measures for a given fabrication process, it cannot be improved further and thus represents a fundamental limit for the operating speed of the comparator according to FIG.
1
.
In the regeneration phase, the voltage difference V
ab
at the nodes A, B of the comparator increases in accordance with the law
V
ab
~
V
beg
·
ⅇ
(
treg
τ
)
where V
beg
is the voltage difference—originating from the amplification phase—at the nodes A, B at the beginning of the regeneration phase, and t
reg
is the duration of the regeneration phase.
A digital switching stage is usually arranged downstream of the comparator of
FIG. 1. A
bit error occurs when, after the regeneration phase has elapsed, V
ab
has not grown large enough to reliably change over the digital switching stage connected downstream. The latter is usually an RS flip-flop which requires set/reset pulses of sufficiently large amplitude and duration at its inputs, since otherwise it does not change over or assumes a metastable state. In both cases, an incorrect decision and thus a bit error can result.
These bit errors can be avoided, in principle, only by choosing the regeneration time t
reg
to be significantly greater than the regeneration time constant &tgr;, in practice usually by a factor of 10-15, and even higher in particularly demanding systems. Consequently, for a given bit error rate and a given semiconductor fabrication process, a specific clock rate of the comparator cannot be exceeded since it is limited by the choice t
reg
>10 . . . 15 &tgr;.
Many contemporary communications systems encounter this technologically imposed limit with data rates in the gigabit/sec range and require comparators which can operate with a very low bit error rate even at clock frequencies in the GHz range. With the known comparator circuit according to
FIG. 1
, even in the case of contemporary CMOS processes with a channel length of 100 nm, the required clock rates of e.g. 4 GHz are regularly not attained, or only with a usually unacceptably high bit error rate.
A possible comparator for input signals with clock rates of a number of GHz is illustrated in FIG.
2
. In this case, here two—it can also be more—comparators from
FIG. 1
are operated in parallel, with inverted clocks CLK, CLKB in each case, so that a doubled, n-fold in the case of n comparators, effective comparison rate results for the same clock rate of the clock CLK.
This embodiment of a multiple comparator is entirely functional, but a number of problems arise. A first problem is that the duplication of the first differential stage
2
means that the capacitive loading on the input nodes IM, IP is also doubled. As a result of this, the current must be more than doubled in a preceding stage in order still to achieve the same signal bandwidth. In practice, this usually leads to an unacceptable power consumption.
A second problem is that a clock-frequency tone arises in the spectrum of the sampled signal as a result of the in practice always different offset voltages of the doubled first differential stages
2
,
2
′ with the transistors M
3
A, M
3
B and M
3
A′, M
3
B′. Particularly when such a comparator is used in a fast A/D converter, e.g. a flash ADC, the so-called SFDR (“Spurious Free Dynamic Range”) of the ADC is thereby impaired.
SUMMARY
Therefore, the object of the present invention is to provide a comparator with a significantly higher comparison rate whilst avoiding the disadvantages mentioned above.
The essential concept of the invention consists in providing the comparator with a plurality of regeneration stages which are connected in parallel and are driven by a first and a second switching arrangement, the parallel regeneration stages being driven in such a way that they operate in a temporally offset manner.
Such a multiphase comparator circuit thus comprises
a first differential stage, to which the signal inputs are fed,
a first switching arrangement, which can optionally connect the output of the first differential stage to the input of a plurality of load circuits,
at least two regeneration stages, which are each connected to one of the load circuits and the first switching arrangement, and
a clock-controlled, second switching arrangement, in order to feed a connectable and disconnectable operating current to the at least two regeneration stages,
the switches of the first and second switching arrangements being driven in such a way that the regeneration stages operate in a temporally offset manner.
In accordance with a preferred embodiment of the invention, a current source for supplying the comparator is provided, which is connected to a common reference node of the first differential stage.
The first or second switching arrangement preferably comprises a plurality of transistors acting as clock-controlled switches, which transistors are preferably fed by a second current source.
In one embodiment of the comparator circuit with two regeneration stages, the first and second switching arrangements are preferably clocked with two clock phases generated from a single clock signal. The two clo

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